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• Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  ...mulator what happens if the GaAsSb/InP junction contains atomic roughness. In this case, momentum conservation is broken and L-valley electrons might eve : Interest in device modeling
  3 KB (377 words) - 15:44, 4 September 2019
• Design study of tunneling transistors based on a core/shell nanowire structures
  ...could provide better performance than standard ones. The key idea consists in using a core/shell nanowire structure where the core and the shell have dif : Interest in device modeling
  3 KB (357 words) - 15:38, 4 September 2019
• Computation of Phonon Bandstructure in III-V Nanostructures
  [[File:Computation of Phonon Bandstructure in III-V Nanostructures.png|280px|thumb]] ...ld's summation method in bulk structures, it is not clear how to handle it in nanostructures without too much increasing the computational burden.
  3 KB (363 words) - 15:37, 4 September 2019
• Simulation of Negative Capacitance Ferroelectric Transistor
  ...ring ON-OFF switching processes. In FETs, the major difficulty to overcome in order to minimize their power consumption is the value of their inverse sub ===Status: In Progress ===
  3 KB (449 words) - 15:37, 4 September 2019
• Investigation of Redox Processes in CBRAM
  ...a large number of different metal/oxide pairs so that their applicability in CBRAM applications can be validated. ...developed an electrochemical model in COMSOL to simulate ON/OFF switching in CBRAM. So far, the model still depends on a number of free input parameters
  4 KB (488 words) - 17:12, 16 September 2021
• Investigation of Metal Diffusion in Oxides for CBRAM Applications
  ...umber of metal/oxide pairs and analyze them regarding their applicability in CBRAM applications ...group has developed a model in COMSOL to simulate ON/OFF switching in CBRAM. So far, the model depends on a number of free input parameters, amon
  3 KB (448 words) - 17:11, 16 September 2021
• Development of an efficient algorithm for quantum transport codes
  :Good knowledge in solid state physics and quantum mechanics ===Status: In Progress ===
  2 KB (284 words) - 17:10, 16 September 2021
• Integrated silicon photonic structures
  physical effect available in integrated photonics circuits has been a scientific and internship project is placed in the heart of our R&D activities and covers topics related
  4 KB (608 words) - 13:58, 23 June 2021
• Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  ...ch means the high purity frequency carriers are required to be synthesized in the range from 15 GHz to even 60 GHz. ...lution (PLL), VCO is the key part of the whole frequency solution since it in general consumes 70% to even 80% of the full power budget of a PLL as well
  4 KB (518 words) - 16:07, 6 May 2019
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  In addition to the "pseudo-processor-controlled approach", the [[Category:In progress]]
  2 KB (326 words) - 12:26, 26 March 2015
• Hardware Support for IDE in Multicore Environment
  [[File:Hardware support for IDE in multicore.jpg|thumb]] ===Status: In Progress ===
  2 KB (188 words) - 10:58, 27 March 2014
• FPGA-Based Digital Frontend for 3G Receivers
  ...n receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received ...s in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE).
  2 KB (348 words) - 20:01, 26 September 2017
• ASIC
  In an ASIC (Application Specific Integrated Circuit) project you will be worki ...nding on the project, your design may be sent for manufacturing to be used in future projects.
  1 KB (165 words) - 19:52, 10 February 2015
• FPGA
  ...prototypes and/or testbeds used to simulate the behavior of large systems. In such a project you will ==Projects in Progress==
  1,020 bytes (132 words) - 19:50, 10 February 2015
• Indoor Positioning with Bluetooth
  : Interest in wireless communications : Knowledge in Matlab, C and/or VHDL is of advantage
  3 KB (449 words) - 12:12, 4 November 2019
• Advanced 5G Repetition Combining
  ...s to a brute-force approach to combining this information. As a first step in your project, you will study ways to reduce the complexity on an algorithmi ===Status: In Progress ===
  3 KB (345 words) - 10:52, 5 April 2022
• OpenRISC SoC for Sensor Applications
  ...cessor design | previous semester thesis]]. We are already using this core in our [[:Category:PULP|multi-core projects]] and we continue to make improvem : SPI is used as a standard interface in many applications, especially in resource limited systems where the number of I/O pins are limited. We alrea
  4 KB (667 words) - 15:23, 23 December 2016
• Hardware Accelerator for Model Predictive Controller
  In the latest years model predictive controller has been successfully applied ...ion enabling the use of model predictive control in a real case scenario. In addition to that thermal evolution of multicore platforms are characterized
  3 KB (456 words) - 08:35, 20 January 2021
• NORX - an AEAD algorithm for the CAESAR competition
  A detailed description of the algorithm can be found in the specification [http://competitions.cr.yp.to/round1/norxv1.pdf PDF]. ===Status: In Progress ===
  3 KB (423 words) - 11:13, 13 June 2014
• Digital Beamforming for Ultrasound Imaging
  ...n body, with both diagnostic and therapeutic applications. IIS is involved in a project developing a high-performance, portable 3D ultrasound platform. ...r elements, it is definitely the computationally most intensive operation. In order to allow for portable 3D ultrasound systems, new algorithms and hardw
  3 KB (423 words) - 11:23, 10 November 2017
• An FPGA-Based Evaluation Platform for Mobile Communications
  In this project you will implement a simulation environment for mobile communi All parts of a wireless receiver have to be carefully optimized in order to
  3 KB (413 words) - 16:05, 21 July 2016
• Real-Time Pedestrian Detection For Privacy Enhancement
  ...n public places are being monitored: real-time surveillance is not allowed in such cases, and stored data can (even for internal use) only be accessed wi : Interest in video processing and machine learning
  3 KB (408 words) - 13:17, 5 February 2016
• Karim Badawi
  == Projects in Progress== category = In progress
  653 bytes (63 words) - 15:06, 5 December 2018
• GSM Voice Capacity Evolution - VAMOS
  ...Evolved EDGE even allows 1 Mobile Station (MS) to use 2 frequency carriers in the downlink. This further provides less time slots available for Voice con ...ections are transmitted simultaneously on the same time slot. This results in 4 simultaneous voice connections if half rate voice codecs are used. The VA
  2 KB (250 words) - 17:45, 14 April 2016
• Design of an LTE Module for the Internet of Things
  ...g low-power and low-cost of IoT components, especially on the client side. In the latest release of the LTE standard, a new user-equipment category (Cat- ...owards Category-0 devices. In a second stage you will implement the design in a hardware description language (HDL) and deploy it to the LTE transceiver
  3 KB (335 words) - 14:20, 4 November 2019
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...n public places are being monitored: real-time surveillance is not allowed in such cases, and stored data can (even for internal use) only be accessed wi
  9 KB (1,289 words) - 19:45, 24 March 2015
• Low-power Clock Generation Solutions for 65nm Technology
  planning a series of [[PULP]] chips in this technology. Depending on the 100 and 800 MHz. In this work, a low power clock generation solution is
  3 KB (466 words) - 19:37, 3 March 2016
• Evaluating the RiscV Architecture
  ...de size etc.) The plan is to manufacture the Risc V based [[PULP]] cluster in UMC 65nm technology, to obtain also measurement results. ===Status: In Progress ===
  3 KB (374 words) - 16:24, 30 October 2020
• Hardware/software co-programming on the Parallella platform
  [[Category:In progress]]
  3 KB (501 words) - 14:26, 2 September 2015
• Gomeza old project4
  ...ency and generality than traditional computer vision techniques. With that in mind, we want to explore their effectiveness on batteryless (e.g. solar-pow ===Status: In Progress ===
  3 KB (480 words) - 19:08, 28 January 2017
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  ...portant as a high-efficiency is controllability: lowest energy consumption in VLSI chips requires several dynamically adaptable voltages: # Unused units need to be fully shut down due to the leakage present even in absence of clock and signal transitions.
  3 KB (438 words) - 18:06, 3 February 2015
• Gomeza old project1
  ...geneity has been a common approach to reach this goal in high-end systems. In this project, your main task will be to design and implement an energy-awar ...rallelism, a typical application can be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, a
  3 KB (431 words) - 18:04, 28 January 2017
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  ...ess sensors are most commonly used for monitoring, detection of events and in general collecting/processing/sending sensors data (i.e temperature, humidi ...sing of the data could be part of the project as well. The project is done in collaboration with Institute of Neuroinformatics Prof. Richard Hahnloser
  4 KB (589 words) - 10:14, 3 August 2018
• Gomeza old project2
  ...ying capacity. By the end of this project a functional node will be tested in a simulated environment. ===Status: In Progress ===
  3 KB (376 words) - 18:04, 28 January 2017
• Energy Neutral Multi Sensors Wearable Device
  ...mount of easily obtained prior information without resorting to supervised in situ training. ===Status: In Progress ===
  2 KB (319 words) - 16:24, 30 October 2020
• Digital
  ...f the time negotiable with the supervisor. Don't hesitate to show interest in a master thesis topic even though you are e.g. looking for a semester thesi ...our projects categories or added a new project, you need to open this page in edit mode and save it (without changing anything) for the list to get refre
  7 KB (811 words) - 15:21, 23 February 2024
• Acceleration and Transprecision
  ...cient. Such accelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cr ===Projects In Progress===
  2 KB (275 words) - 17:05, 24 November 2023
• Telecommunications
  ...telecommunications. Feel free to contact them if you want to do a project in this field. ==Projects in Progress==
  892 bytes (86 words) - 17:42, 24 March 2015
• Ultrafast Medical Ultrasound imaging on a GPU
  In conventional ultrasound imaging each image line is acquired sequentially. S In ultrafast imaging, on the other hand, the entire field of view is acquired
  3 KB (428 words) - 12:13, 1 August 2018
• Philipp Schönle
  ==Projects in Progress== category = In progress
  569 bytes (54 words) - 10:52, 10 March 2015
• Benjamin Sporrer
  ==Projects in Progress== category = In progress
  567 bytes (54 words) - 13:01, 10 March 2015
• Real-Time Optical Flow Using Neural Networks
  ...others work by looking at few well-trackable points (corners, edges, ...) in both images to find correspondences and then solve complex optimization pro ...re computer vision is most interesting: on low-power and mobile platforms, in cars, ...
  5 KB (707 words) - 11:22, 5 February 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...re virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires the programmer to manual ...TCDM to filter the accelerator's accesses to shared data structures living in main memory, and to spare the programmer from manually setting up the DMA t
  5 KB (716 words) - 13:43, 29 November 2019
• DigitalUltrasoundHead
  ...r a large cable containing hundreds of small coaxial cables. This is shown in the figure below: We plan to replace this analog connection by a digital link as shown in the next figure:
  3 KB (378 words) - 11:52, 10 January 2017
• Audio
  ==Projects in Progress== category = In progress
  403 bytes (36 words) - 17:28, 11 February 2015
• Pascal Hager
  == Projects in Progress== category = In progress
  775 bytes (81 words) - 11:40, 10 November 2017
• Software
  In this category the projects require you to do programming ==Projects in Progress==
  473 bytes (46 words) - 13:45, 8 August 2016
• Vector Processor for In-Memory Computing
  ...ors - and these would have direct access to the DRAM. The concept of such "in-memory computing" ...so far it has not been viable on an industrial scale. Recent developments in process technology combined with industrial efforts to bring them
  3 KB (443 words) - 13:10, 2 November 2015
• Signal to Noise Ratio Estimation for 3G standards
  ...to-noise ratio (SNR) is the basis for almost any digital signal processing in a receiver. ...semester project you will implement an efficient SNR-estimation algorithm in order to obtain an energy and area-efficient solution. This can be done as
  2 KB (300 words) - 11:23, 14 April 2016
• FFT-based Convolutional Network Accelerator
  ...or FPGA accelerator to perform this step faster and more power-efficiently in the frequency domain. * Interest in computer vision, signal processing and VLSI design
  8 KB (1,145 words) - 11:30, 5 February 2016

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