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• Structural Health Monitoring (SHM) System (1-2S)
  #REDIRECT [[Structural Health Monitoring (SHM) System (1-2S/M)]]
  64 bytes (9 words) - 11:47, 14 May 2024
• Intelligent Disaster Early-Warning System (1-2S/M)
  ...on of your project will be the development of a sophisticated notification system designed to automatically alert both local authorities and the public about * '''Automated Warning System:''' Develop a notification system that automatically alerts local authorities and the public of potential dan
  4 KB (531 words) - 17:09, 16 May 2024

Page text matches

• PULP
  [[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]] * [http://asic.ethz.ch/2020/Thestral.html Thestral] Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed t
  10 KB (1,563 words) - 10:09, 19 August 2022
• Indoor Positioning with Bluetooth
  [[Category:System Design]]
  3 KB (449 words) - 12:12, 4 November 2019
• OpenRISC SoC for Sensor Applications
  ...r OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can co : For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the
  4 KB (667 words) - 15:23, 23 December 2016
• Hardware Accelerator for Model Predictive Controller
  In recent years reseach works shows that thermal evolution of a multicore system can be effectively modelled with linear state-space representation enabling ...will then be part of a larger system and be part of the thermal management system. In this project the goal is to implement a novel MPC algorithm in hardware
  3 KB (456 words) - 08:35, 20 January 2021
• 4th Generation Synchronization
  ..., R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/0
  2 KB (350 words) - 17:56, 14 April 2016
• Analog
  ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ...f wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmis
  3 KB (369 words) - 18:11, 1 March 2023
• Ambient RF Energy harvesting for Wireless Sensor Network
  ...method by implementing our system.. Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe : Interest in Computer Architectures at system level
  3 KB (378 words) - 19:56, 9 February 2015
• Android reliability governor
  Reliability (R(t)) is the probability that a given system does not fail before time t. It is becoming a major concern in modern multi ...bile]] [[Category:Temperature]] [[Category:Dynamic Management]] [[Category:System Design]]
  4 KB (573 words) - 17:24, 9 February 2015
• Thermal Control of Mobile Devices
  ...s an heterogeneous thermal profile which is highly dependent on the actual system usage. As a matter of fact today and future mobile devices are thermally li ...thermal model can be directly identified from the target device by mean of system identification and self-calibrating routines.
  3 KB (452 words) - 11:03, 10 February 2015
• Real-Time Pedestrian Detection For Privacy Enhancement
  [[Category:System Design]]
  3 KB (408 words) - 13:17, 5 February 2016
• Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
  ...stem was proposed alongside the release-8 of the Long Term Evolution (LTE) system for the fourth generation (4G) of mobile communication. While the air inter ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf
  1 KB (159 words) - 11:16, 23 September 2016
• Digital Transmitter for Cellular IoT
  [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo
  3 KB (384 words) - 16:41, 17 July 2016
• Design of an LTE Module for the Internet of Things
  ...E transceiver [2] will be used. You will start with your design by doing a system analysis on the required building blocks (Synchronization, FFT, Symbol dete [[Category:System Design]]
  3 KB (335 words) - 14:20, 4 November 2019
• Active-Set QP Solver on FPGA
  : Matlab, C++, VHDL or System Verilog
  2 KB (351 words) - 13:09, 2 November 2015
• LAPACK/BLAS for FPGA
  : Matlab, C++, VHDL or System Verilog
  2 KB (328 words) - 12:38, 1 June 2017
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  ...er, a careful design of each regulator is extremely important. A PCB-based system, containing of-the-shelf converter chips where available, and discrete-comp [[Category:System Design]]
  3 KB (438 words) - 18:06, 3 February 2015
• Gomeza old project1
  ...be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, and reduce the total energy consumption.
  3 KB (431 words) - 18:04, 28 January 2017
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  [[Category:System Design]]
  4 KB (589 words) - 10:14, 3 August 2018
• Energy Neutral Multi Sensors Wearable Device
  : Interest in Computer Architectures at system level : Wearable system I (prof. Troester lectures)
  2 KB (319 words) - 16:24, 30 October 2020
• Real-Time Stereo to Multiview Conversion
  [[File:mvSystem.jpg|thumb|600px|a) Multiview system in action and b) closeup of the hardware prototype.]] Ideally, a 3D display system should not require the users to
  3 KB (509 words) - 09:09, 23 October 2015
• Digital
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  7 KB (816 words) - 11:57, 8 May 2024
• Modeling FlooNoC in GVSoC (S/M)
  ...event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). It plays a crucial role in enabling agile design space exp * Experience with System Verilog is recommended but not strictly necessary
  4 KB (520 words) - 15:15, 4 December 2023
• Time and Frequency Synchronization in LTE Cat-0 Devices
  ...k, Nitin Mangalvedhe, Amitava Ghosh, and Benny Vejlgaard. Narrowband LTE-M system for M2M communication. 2014.
  4 KB (561 words) - 10:43, 6 November 2017
• Baseband Meets CPU
  is indispensable. Ideally, System-on-a-Chip (SoC) or System-in-a-Package (SiP) modems such as [1] are
  7 KB (1,105 words) - 20:02, 26 September 2017
• Real-Time Optical Flow Using Neural Networks
  [[Category:Digital]] [[Category:System Design]]
  5 KB (707 words) - 11:22, 5 February 2016
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
  [[Category:System Design]]
  1 KB (169 words) - 16:42, 9 December 2015
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.
  5 KB (716 words) - 13:43, 29 November 2019
• DigitalUltrasoundHead
  ...e piezoelectric elements in the transducer head are connected to a backend system over a large cable containing hundreds of small coaxial cables. This is sho In order to do so, the entire analog frontend of the ultrasound system needs to be integrated into the transducer head and a digital link needs to
  3 KB (378 words) - 11:52, 10 January 2017
• High-speed Scene Labeling on FPGA
  ...tation of an entire scene labeling network. In order to keep the developed system flexible in terms of the convolutional neural network that is applied as we ...rt software blocks to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.
  8 KB (1,197 words) - 18:18, 29 August 2016
• Time Synchronization for 3G Mobile Communications
  [[Category:System Design]]
  3 KB (420 words) - 11:22, 14 April 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e This system design project requires work to be done at several layers of abstraction. M
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e : VHDL/System Verilog, C
  4 KB (554 words) - 17:57, 7 November 2017
• Autonomous Sensing For Trains In The IoT Era
  ...ment of novel zero-power sensors that act as a trigger for the rest of the system when an important event is detected and consume zero-power between two dete ...classification accuracy and energy efficiency and to further optimize the system.
  6 KB (774 words) - 08:36, 23 November 2022
• Switched Capacitor Based Bandgap-Reference
  [[Category:System Design]] [[Category:System Design]]
  4 KB (471 words) - 11:13, 3 May 2018
• Compressed Sensing for Wireless Biosignal Monitoring
  ...we have implemented and fabricated an 8-channel biosignal acquisition SoC (System-on-Chip) [http://asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including ana
  2 KB (353 words) - 08:35, 20 January 2021
• Scattering Networks for Scene Labeling
  [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Luk [[Category:Digital]] [[Category:System Design]]
  4 KB (563 words) - 11:29, 5 February 2016
• Autonomous Smart Watches: Hardware and Software Desing
  ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level
  3 KB (448 words) - 11:59, 28 July 2015
• A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  : Interest in Computer Architectures at system level ...arning would be beneficial (i.e. semester project or exam done in Wearable system I prof. Troester)
  3 KB (380 words) - 11:59, 28 July 2015
• Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  [[Category:System Design]]
  4 KB (507 words) - 12:11, 16 February 2016
• Low Power Neural Network For Multi Sensors Wearable Devices
  ...otal power spent for event detection, we propose an alternative, two-stage system architecture consisting of: 1. "wake-up sensing" (WUS) circuit, and 2. main [[Category:System Design]]
  7 KB (895 words) - 17:02, 28 July 2017
• Improving our Smart Camera System
  ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]
  8 KB (1,176 words) - 16:26, 30 October 2020
• Eye movements
  ...by canceling self-induced motion blur. The VOR is driven by the vestibular system and induces short-latency eye movements in the opposite direction to the he
  2 KB (376 words) - 14:43, 29 July 2015
• VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
  ...l-diversity streams have been introduced with the Evolved EDGE 2G cellular system [1], the recent EC-GSM-IoT standard achieves up to 20 dB coverage extension
  3 KB (418 words) - 10:39, 6 November 2017
• Beat DigRF
  ...ration of the communication portion of the node is indispensable. Ideally, System-on-a-Chip (SoC) modems are used.
  2 KB (299 words) - 17:58, 14 April 2016
• Implementing Hibernation on the ARM Cortex M0
  [[Category:System Design]]
  3 KB (390 words) - 11:59, 20 June 2016
• Ultra-Efficient Visual Classification on Movidius Myriad2
  [[Category:System Design]]
  4 KB (593 words) - 14:57, 30 November 2016
• Efficient Implementation of an Active-Set QP Solver for FPGAs
  ...lly, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the corresponding software inter : Matlab, C++, VHDL or System Verilog
  4 KB (542 words) - 12:39, 1 June 2017
• Design of State Retentive Flip-Flops
  ...stablished method to save power in circuit parts currently not in use in a system on chip (SoC). In contrast to clock gating, where the clock signal is disab
  2 KB (364 words) - 09:34, 25 July 2017
• Standard Cell Compatible Memory Array Design
  Memories are central building blocks of any processing system, in fact most of the performance of a modern processor is determined by its
  5 KB (769 words) - 15:54, 23 May 2018
• Development of a Rockfall Sensor Node
  [[Category:System Design]]
  2 KB (340 words) - 11:55, 21 August 2018

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