Search results

Create the page "Pschiavo" on this wiki! See also the search results found.

Page title matches

• User:Pschiavo
  * '''e-mail''': [mailto:pschiavo@iis.ee.ethz.ch pschiavo@iis.ee.ethz.ch]
  2 KB (192 words) - 17:22, 15 August 2022

Page text matches

• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  : Supervision: [[:User:Fconti | Francesco Conti]], [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Fschuiki | Fabian Schuiki]]
  6 KB (949 words) - 13:41, 10 November 2020
• User:Pschiavo
  * '''e-mail''': [mailto:pschiavo@iis.ee.ethz.ch pschiavo@iis.ee.ethz.ch]
  2 KB (192 words) - 17:22, 15 August 2022
• Extend the RI5CY core with priviledge extensions
  : Supervision: [[:User:Pschiavo | Pasquale Davide Schiavone]] [[Category:Pschiavo]]
  4 KB (661 words) - 08:38, 20 January 2021
• Design of Scalable Event-driven Neural-Recording Digital Interface
  : Supervision: [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Adimauro | Alfio Di Mauro]], [[:User
  8 KB (1,269 words) - 18:40, 5 September 2019
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  : Supervision: [[:User:Pschiavo | Pasquale Davide Schiavone]] [[Category:Pschiavo]]
  7 KB (1,030 words) - 19:05, 29 January 2021
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  : Supervision: [[:User:Fconti | Francesco Conti]] <!--, [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Fschuiki | Fabian Schuiki]]-->
  7 KB (961 words) - 21:21, 29 January 2019
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  : Supervision: [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Balasar | Robert Balas]], [[:User:Za
  4 KB (574 words) - 08:42, 20 January 2021
• Heroino: Design of the next CORE-V Microcontroller
  : Supervision: [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Zarubaf|Florian Zaruba]]
  9 KB (1,314 words) - 00:01, 7 February 2021
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  : Supervision: [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Balasar | Robert Balas]] [[Category:Pschiavo]]
  4 KB (589 words) - 19:19, 29 January 2021
• Ibex: FPGA Optimizations
  : Supervision: [[:User:Vogelpi|Pirmin Vogel]], [[:User:Pschiavo | Pasquale Davide Schiavone]]
  5 KB (666 words) - 09:45, 28 August 2020
• Ibex: Bit-Manipulation Extension
  : Supervision: [[:User:Vogelpi|Pirmin Vogel]], [[:User:Pschiavo | Pasquale Davide Schiavone]]
  4 KB (639 words) - 09:45, 28 August 2020
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  ...eggiman | Manuel Eggimann]] [[:User:Paulin | Gianna Paulin]] <!--, [[:User:Pschiavo | Pasquale Davide Schiavone]], [[:User:Fschuiki | Fabian Schuiki]]-->
  7 KB (1,032 words) - 15:31, 16 November 2020
• Energy Efficient SoCs
  ===[[:User:Pschiavo |Davide Schiavone]]===
  3 KB (339 words) - 15:59, 1 November 2023
• Ibex: Tightly-Coupled Accelerators and ISA Extensions
  ...er:sriedel|Samuel Riedel]], [[:User:Matheusd|Matheus Cavalcante]], [[:User:Pschiavo | Pasquale Davide Schiavone]]
  6 KB (835 words) - 12:52, 27 April 2021
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
  [[Category:Pschiavo]] ** [[:User:Pschiavo | Pasquale Davide Schiavone]]
  8 KB (1,304 words) - 14:44, 23 October 2023