Pages that link to "Coding Guidelines"
From iis-projects
The following pages link to Coding Guidelines:
View (previous 100 | next 100) (20 | 50 | 100 | 250 | 500)- Accelerator for Boosted Binary Features (← links)
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen (← links)
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf (← links)
- Glitches Reduce Listening Time of Your iPod (← links)
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator (← links)
- Audio DAC Conversion Jitter Measurement System (← links)
- Android Software Design (← links)
- Investigation of the source starvation effect in III-V MOSFET (← links)
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs) (← links)
- Design study of tunneling transistors based on a core/shell nanowire structures (← links)
- Computation of Phonon Bandstructure in III-V Nanostructures (← links)
- Simulation of Negative Capacitance Ferroelectric Transistor (← links)
- Hardware Support for IDE in Multicore Environment (← links)
- OpenRISC SoC for Sensor Applications (← links)
- Image Sensor Interface and Pre-processing (← links)
- Hardware Accelerator for Model Predictive Controller (← links)
- NORX - an AEAD algorithm for the CAESAR competition (← links)
- Ambient RF Energy harvesting for Wireless Sensor Network (← links)
- Infrared Wake Up Radio (← links)
- Android reliability governor (← links)
- Thermal Control of Mobile Devices (← links)
- Real-Time Pedestrian Detection For Privacy Enhancement (← links)
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC (← links)
- Low-power Clock Generation Solutions for 65nm Technology (← links)
- Evaluating the RiscV Architecture (← links)
- Active-Set QP Solver on FPGA (← links)
- LAPACK/BLAS for FPGA (← links)
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip (← links)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (← links)
- Receiver design for the DigRF 4G high speed serial link (← links)
- Gomeza old project1 (← links)
- Gomeza old project2 (← links)
- Real-Time Optical Flow Using Neural Networks (← links)
- Energy Neutral Multi Sensors Wearable Device (← links)
- Vector Processor for In-Memory Computing (← links)
- FFT-based Convolutional Network Accelerator (← links)
- High-speed Scene Labeling on FPGA (← links)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (← links)
- DMA Streaming Co-processor (← links)
- Spatio-Temporal Video Filtering (← links)
- Switched Capacitor Based Bandgap-Reference (← links)
- Autonomous Smart Watches: Hardware and Software Desing (← links)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (← links)
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors (← links)
- Kinetic Energy Harvesting For Autonomous Smart Watches (← links)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (← links)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (← links)
- Development of a Rockfall Sensor Node (← links)
- Gomeza old project3 (← links)
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node (← links)
- Bateryless Heart Rate Monitoring (← links)
- Low Power Neural Network For Multi Sensors Wearable Devices (← links)
- Rethinking our Convolutional Network Accelerator Architecture (← links)
- Using Motion Sensors to Support Indoor Localization (← links)
- Design of a VLIW processor architecture based on RISC-V (← links)
- Minimal Cost RISC-V core (← links)
- Design of a Fused Multiply Add Floating Point Unit (← links)
- Gomeza old project4 (← links)
- Towards Self Sustainable UAVs (← links)
- Ultra Low Power Conversion Circuit For Batteryless Applications (← links)
- Gomeza old project5 (← links)
- Towards The Integration of E-skin into Prosthetic Devices (← links)
- A Wireless Sensor Network for a Smart Building Monitor and Control (← links)
- A Wearable System To Control Phone And Electronic Device Without Hands (← links)
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks (← links)
- Charging System for Implantable Electronics (← links)
- Bringing XNOR-nets (ConvNets) to Silicon (← links)
- Improving our Smart Camera System (← links)
- Ultra Low-Power Oscillator (← links)
- High performance continous-time Delta-Sigma ADC for biomedical applications (← links)
- Design of low-offset dynamic comparators (← links)
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications (← links)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy (← links)
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT (← links)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (← links)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (← links)
- Design of Charge-Pump PLL in 22nm for 5G communication applications (← links)
- Sensor Fusion for Rockfall Sensor Node (← links)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea (← links)
- Towards Online Training of CNNs: Hebbian-Based Deep Learning (← links)
- Single-Bit-Synapse Spiking Neural System-on-Chip (← links)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (← links)
- Tiny CNNs for Ultra-Efficient Object Detection on PULP (← links)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (← links)
- Autonomous Sensing For Trains In The IoT Era (← links)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (← links)
- 5G Cellular RF Front-end Design in 22nm CMOS Technology (← links)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing (← links)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (← links)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (← links)
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams (← links)
- A computational memory unit using phase-change memory devices (← links)
- Deep Learning for Brain-Computer Interface (← links)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (← links)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (← links)
- Trace Debugger for custom RISC-V Core (← links)
- Efficient Search Design for Hyperdimensional Computing (← links)
- Creating a HDMI Video Interface for PULP (← links)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (← links)
- Hyper Meccano: Acceleration of Hyperdimensional Computing (← links)