Difference between revisions of "User:Pschiavo"
From iis-projects
(→Pasquale Davide Schiavone) |
(→Available projects) |
||
(14 intermediate revisions by the same user not shown) | |||
Line 3: | Line 3: | ||
− | Pasquale Davide Schiavone is a PhD student at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. | + | Pasquale Davide Schiavone is a PostDoc at the Embedded System Laboratory at EPF Lausanne, and former PhD student at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. |
He obtained a BSc. and a MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016 respectively. | He obtained a BSc. and a MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016 respectively. | ||
His main research focus is on low-power energy-efficient computer architectures for Internet-Of-Things systems and brain-machine interfaces through EEG and neural action potential signals. | His main research focus is on low-power energy-efficient computer architectures for Internet-Of-Things systems and brain-machine interfaces through EEG and neural action potential signals. | ||
− | |||
− | |||
== '''Interests''' == | == '''Interests''' == | ||
Line 19: | Line 17: | ||
== '''Available projects''' == | == '''Available projects''' == | ||
+ | |||
+ | * [[MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.]] (semester/master thesis) | ||
+ | * [[Heroino: Design of the next CORE-V Microcontroller]] (semester/master thesis) | ||
+ | * [[Design of Scalable Event-driven Neural-Recording Digital Interface]] (semester/master thesis) | ||
* [[Design of Scalable Event-driven Neural-Recording Digital Interface]] (semester/master thesis) | * [[Design of Scalable Event-driven Neural-Recording Digital Interface]] (semester/master thesis) | ||
− | |||
− | |||
* If you have your personal idea, you can also contact me for projects! | * If you have your personal idea, you can also contact me for projects! | ||
Line 28: | Line 28: | ||
== '''Contact Information''' == | == '''Contact Information''' == | ||
− | * '''Office''': | + | * '''Office''': J89 |
* '''e-mail''': [mailto:pschiavo@iis.ee.ethz.ch pschiavo@iis.ee.ethz.ch] | * '''e-mail''': [mailto:pschiavo@iis.ee.ethz.ch pschiavo@iis.ee.ethz.ch] |
Latest revision as of 17:22, 15 August 2022
Contents
Pasquale Davide Schiavone
Pasquale Davide Schiavone is a PostDoc at the Embedded System Laboratory at EPF Lausanne, and former PhD student at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. He obtained a BSc. and a MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016 respectively. His main research focus is on low-power energy-efficient computer architectures for Internet-Of-Things systems and brain-machine interfaces through EEG and neural action potential signals.
Interests
- Computer and System Architecture
- Digital ASIC Design
- Embedded systems
- Heterogeneous multicore architectures for energy-efficient and low-power embedded systems
- Brain-Machine interface
Available projects
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (semester/master thesis)
- Heroino: Design of the next CORE-V Microcontroller (semester/master thesis)
- Design of Scalable Event-driven Neural-Recording Digital Interface (semester/master thesis)
- Design of Scalable Event-driven Neural-Recording Digital Interface (semester/master thesis)
- If you have your personal idea, you can also contact me for projects!
Completed projects
- Deep Learning for Brain-Computer Interface (semester thesis)
Contact Information
- Office: J89
- e-mail: pschiavo@iis.ee.ethz.ch