User contributions
From iis-projects
- 17:35, 10 December 2021 diff hist +69 Implementing DSP Instructions in Banshee (1S)
- 23:34, 19 November 2021 diff hist +114 Streaming Integer Extensions for Snitch (M)
- 23:33, 19 November 2021 diff hist +9,969 N Implementing DSP Instructions in Banshee (1S) Created page with "<!-- Implementing DSP Instructions in Banshee (M/1S) --> = Overview = == Status: Available == * Type: Semester Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :..."
- 17:20, 2 August 2021 diff hist +20 Fast Simulation of Manycore Systems (1S) current
- 17:19, 2 August 2021 diff hist +30 Fast Simulation of Manycore Systems (1S)
- 17:18, 2 August 2021 diff hist -8 Fast Simulation of Manycore Systems (1S)
- 17:18, 2 August 2021 diff hist -3 Fast Simulation of Manycore Systems (1S)
- 17:16, 2 August 2021 diff hist +9,702 N Fast Simulation of Manycore Systems (1S) Created page with "<!-- Fast Simulation of Manycore Systems (1S) --> = Overview = == Status: Available == * Type: Semester Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sr..."
- 17:14, 2 August 2021 diff hist +4 Efficient Synchronization of Manycore Systems (M/1S)
- 10:41, 6 July 2021 diff hist -4 Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) current
- 10:41, 6 July 2021 diff hist -4 Manycore System on FPGA (M/S/G) current
- 00:08, 13 March 2021 diff hist -4 ISA extensions in the Snitch Processor for Signal Processing (M) current
- 00:07, 13 March 2021 diff hist 0 Transforming MemPool into a CGRA (M)
- 00:06, 13 March 2021 diff hist +4 Transforming MemPool into a CGRA (M)
- 18:47, 15 February 2021 diff hist +18 Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- 11:50, 5 February 2021 diff hist +13 Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- 11:46, 5 February 2021 diff hist +22 Manycore System on FPGA (M/S/G)
- 18:03, 31 January 2021 diff hist -7 Manycore System on FPGA (M/S/G)
- 18:02, 31 January 2021 diff hist +4 Manycore System on FPGA (M/S/G) →Project Description
- 18:02, 31 January 2021 diff hist 0 Manycore System on FPGA (M/S/G)
- 17:58, 31 January 2021 diff hist +1,686 Manycore System on FPGA (M/S/G)
- 17:18, 31 January 2021 diff hist 0 N File:Mempool logo.pdf current
- 17:12, 31 January 2021 diff hist -1 Transforming MemPool into a CGRA (M)
- 17:12, 31 January 2021 diff hist -2 Transforming MemPool into a CGRA (M)
- 17:10, 31 January 2021 diff hist +4 Transforming MemPool into a CGRA (M) →Introduction
- 17:10, 31 January 2021 diff hist 0 N File:Mempool cgra.png current
- 17:08, 31 January 2021 diff hist +13,058 N Transforming MemPool into a CGRA (M) Created page with "<!-- Transforming MemPool into a CGRA (M) --> = Overview = == Status: Available == * Type: Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sriedel..."
- 00:46, 31 January 2021 diff hist +6,925 N Manycore System on FPGA (M/S/G) Created page with "<!-- Manycore System on FPGA --> = Overview = == Status: Available == * Type: Bachelor/Semester/Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sri..."
- 19:19, 29 January 2021 diff hist -18 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core current
- 19:16, 29 January 2021 diff hist -18 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 19:15, 29 January 2021 diff hist 0 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 19:13, 29 January 2021 diff hist -1 ASIC Design Projects →How does it work current
- 19:12, 29 January 2021 diff hist +18 VLSI Implementation of a 5G Ciphering Accelerator
- 19:10, 29 January 2021 diff hist +18 Event-Driven Convolutional Neural Network Modular Accelerator →Links current
- 19:10, 29 January 2021 diff hist +18 Spiking Neural Network for Autonomous Navigation →Links current
- 19:10, 29 January 2021 diff hist +18 RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB →Links current
- 19:10, 29 January 2021 diff hist +18 Level Crossing ADC For a Many Channels Neural Recording Interface →Links current