Search results

Create the page "FPGA & Digital ASIC Design" on this wiki! See also the search results found.

• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  In this project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient cont : 40% Architecture Design
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  # Specification, RTL design and host software development of a trace debugger for one of our custom RIS # FPGA evaluation of your implementation.
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  ...arch operations in HD computing. You would develop RTL implementation with FPGA prototyping. : Architecture Design
  3 KB (366 words) - 15:39, 10 November 2020
• Creating a HDMI Video Interface for PULP
  ...ted native differential signalling this is easier to implement in a purely digital fashion. ...ip (or external) frame-buffer. At first your implementation will target an FPGA (Xilinz Zynq) implementation as a first prototype but upon successful compl
  4 KB (603 words) - 09:37, 10 July 2018
• BigPULP: Multicluster Synchronization Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (VHDL, FPGA/ASIC Design, C)
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (C, VHDL, FPGA/ASIC Design)
  6 KB (801 words) - 15:05, 23 August 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  * '''[[Design Review]]''' [[Category:Digital]]
  3 KB (409 words) - 13:58, 9 November 2017
• IoT Turbo Decoder
  [[File:High Throughput Turbo Decoder Design.png|400px|thumb|A previous, high throughput, Turbo Decoder developed at IIS ...processor cluster. The final design can either be mapped to an FPGA, or an ASIC.
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...phys.ethz.ch/ Physics Department of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real world, t ...puts that connect to the AC701’s FMC connector and get familiar with the design of the unit and it’s purpose.
  4 KB (460 words) - 21:42, 30 January 2018
• Wireless Communication Systems for the IoT
  ...ns, which incorporate analog sensor / actuator front ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip ...an RF SoC design is the hardware- and energy-efficient realization of the digital baseband algorithms in which we constantly offer various semester and maste
  3 KB (344 words) - 01:45, 10 February 2021
• HERO: TLB Invalidation
  ...evaluation platform combines a modern ARMv8 multicluster CPU with a Xilinx FPGA capable of implementing PULP with up to 8 clusters and a total of 64 cores. : 50% Design and Implementation (SystemVerilog, C, FPGA/ASIC Design)
  6 KB (796 words) - 17:19, 18 November 2019
• Beat Cadence
  ...g a highly integrated SoC for the IoT in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost ...s project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a mac
  1 KB (217 words) - 11:01, 18 March 2019
• Aliasing-Free Wavetable Music Synthesizer
  [[File:Iip_syneth.png|300px|thumb|SYNƎTH wavetable synthesizer ASIC project. ]] ...integrated circuits (ASICs). Furthermore, it is practically challenging to design wavetable oscillators that do not produce aliasing artifacts, especially if
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  ...a large number of freely programmable operators resulting in endless sound-design possibilities compared to existing FM synthesizers. ...he architecture in a modern CMOS process and send the modular FM synthesis ASIC to fabrication.
  5 KB (549 words) - 12:35, 28 November 2022
• Hyperdimensional Computing
  * '''Algorithmic''' design and optimizations (Matlab/ Python) * '''Hardware and digital architecture''' design
  10 KB (1,341 words) - 10:46, 25 April 2018
• CMOS power amplifier for field measurements in MRI systems
  .... The thesis offers the possibility to study main aspects of analog and RF design, such as noise, linearity, matching, small signal-concepts and power consum : 50% Design
  3 KB (354 words) - 16:06, 6 May 2019
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...ecord and display the signal processing results. The interface between the FPGA and ADC board, DDR3 and PC is already implemented. ...with signal processing in the context of quantum computing experiments and FPGA hardware implementations
  5 KB (599 words) - 09:03, 21 December 2017
• Inductive Charging Circuit for Implantable Devices
  : 30% Design * '''[[Design Review]]'''
  3 KB (329 words) - 11:43, 20 August 2021
• Extend the RI5CY core with priviledge extensions
  ...plus custom instructions that have been designed to efficiently deal with digital-signal-processing applications typical for near-sensor systems. ...lace. The student will focus especially on the memory exeptions and in the design of an MMU. The student is required to extend the testbench to emulated the
  4 KB (661 words) - 08:38, 20 January 2021
• Wearables for Sports and Life Enhancement
  : 40% ASIC Design * '''[[Design Review]]'''
  3 KB (381 words) - 14:17, 28 January 2023

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)