[[Category:High Performance SoCs]]
...-up-table (LUT) and an addition. That can significantly reduce the overall computing and energy needs.
6 KB (823 words) - 16:32, 3 November 2022
...SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators.
3 KB (339 words) - 15:59, 1 November 2023
...dware acceleration of transformer models poses new challenges due to their high arithmetic intensities, large memory requirements, and complex dataflow dep
...rallelism of attention mechanism and 8-bit integer quantization to improve performance and energy efficiency. To maximize ITA’s energy efficiency, we focus on m
3 KB (485 words) - 10:52, 12 December 2023
...eless communication, where massive amounts of data need to be processed at high rates.
[[Category:Event-Driven Computing]]
7 KB (882 words) - 14:33, 28 July 2021
[[Category:High Performance SoCs]]
...ating systems (OSes) – a common technique used in secure systems and cloud computing to allow running untrusted OSes or multiple OSes in parallel.
3 KB (391 words) - 08:49, 21 June 2022
...ty limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated.
...nts on phase-change memory chips comprising more than 1 million devices to high-level algorithmic development in a deep learning framework such as TensorFl
5 KB (628 words) - 12:51, 17 April 2020
...activity in their field of view, they send an alarm to a centralized high-performance vision platform, which is able to pan, tilt and zoom its field of view to t
...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
3 KB (433 words) - 15:36, 4 August 2022
[[Category:High Performance SoCs]]
...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
4 KB (557 words) - 16:14, 6 November 2022
...ss communication, in which massive amounts of data need to be processed at high rates.
[[Category:Event-Driven Computing]]
7 KB (933 words) - 19:29, 21 November 2021
[[Category:High Performance SoCs]]
...lerator interface, allowing it to be paired with a powerful FPU to achieve high FPU utilizations and compute-over-control ratio.
8 KB (1,220 words) - 15:18, 9 July 2021
[[Category:High Performance SoCs]]
...-up-table (LUT) and an addition. That can significantly reduce the overall computing and energy needs.
6 KB (846 words) - 16:50, 3 November 2022
[[Category:High Performance SoCs]]
To realize the performance potential of many-core
6 KB (897 words) - 19:52, 22 February 2024
...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program
...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
6 KB (801 words) - 15:05, 23 August 2018
...f 12 SHAVE processors, that leverage VLIW and SIMD operations to achieve a high level of energy efficiency. The SHAVE processors share a 2MB tightly couple
# Measurement of performance and energy efficiency of the proposed solution
4 KB (593 words) - 14:57, 30 November 2016
...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program
...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
6 KB (805 words) - 12:17, 22 January 2018
[[Category:High Performance SoCs]]
...d supercomputing to industrial automation and avionics, including embedded computing products that nowadays feature at least one Ethernet interface. Ethernet st
5 KB (631 words) - 09:28, 3 November 2023
...hitecture. We will use a state of the art 28nm SOI process to evaluate the performance of the processor.
====Energy Efficient Computing using Multicore Systems====
10 KB (1,669 words) - 19:01, 30 January 2014
[[Category:High Performance SoCs]]
...f 1024 Snitch cores, having 4096 banks of shared memory. The huge parallel computing power and the small latency cost of the shared memory accesses in TeraPool
3 KB (460 words) - 18:54, 9 November 2022
...hardware and provide features such as efficient interrupt nesting to allow high priority interrupts to get the highest attention. On the software-level you
Measure the performance impact, interrupt latency and jitter.
4 KB (508 words) - 18:59, 10 January 2022
[[Category:High Performance SoCs]]
...f 1024 Snitch cores, having 4096 banks of shared memory. The huge parallel computing power of TeraPool suits perfectly the purpose of accelerating embarrassingl
3 KB (490 words) - 10:38, 2 November 2023
