Latest revision as of 14:43, 23 October 2023

Overview

Status: Expired

• Type: 2 Semester Thesis or 1 Master Thesis
• Professor: Prof. Dr. Luca Benini
• Supervisors:
  • Tim Fischer: fischeti@iis.ee.ethz.ch
  • Michael Rogenmoser: michaero@iis.ee.ethz.ch

Introduction

As the number of computing cores and accelerators on a single chip is rapidly growing, there is a rising need for scalable, high-bandwidth, and low-latency on-chip communication fabrics. This need is often addressed by deploying networks-on-chip (NoCs) through which the compute cores can communicate, similar to how computers can communicate through the Internet. The nodes that are connected to the NoC usually communicate with (e.g., AMBA AXI, TCDM) that cannot be used on the network layer, hence requiring protocol translation at the border.

Project

In our group, we are currently developing an NoC that can interface with all the AXI IPs we have developed so far in our group. The goal of this project would be to build a system with a mesh NoC and a couple of cores and do the system integration for a potential tapeout. For the verification, low-level software and drivers should be written and tested

Character

• 30% System Integration
• 20% Verification
• 20% Low-level software and drivers
• 30% Backend implementation

Prerequisites

• Experience with System Verilog, VLSI 1
• Experience with physical implementation, VLSI 2
• C programming language experience