User contributions
From iis-projects
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- 16:05, 24 November 2023 (diff | hist) . . (-271) . . Acceleration and Transprecision (current)
- 16:04, 24 November 2023 (diff | hist) . . (+56) . . Hardware Acceleration (current)
- 16:03, 24 November 2023 (diff | hist) . . (+22) . . Hardware Acceleration (→Matteo Perotti)
- 16:03, 24 November 2023 (diff | hist) . . (-84) . . Hardware Acceleration (→Computational Units)
- 16:02, 24 November 2023 (diff | hist) . . (0) . . Hardware Acceleration (→Computational Units)
- 16:02, 24 November 2023 (diff | hist) . . (+24) . . Hardware Acceleration
- 16:01, 24 November 2023 (diff | hist) . . (-182) . . m Hardware Acceleration
- 16:02, 3 November 2023 (diff | hist) . . (-500) . . Deep Learning Projects
- 16:00, 3 November 2023 (diff | hist) . . (-77) . . User:Fischeti (current)
- 11:48, 3 November 2023 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (current)
- 11:48, 3 November 2023 (diff | hist) . . (+104) . . Efficient collective communications in FlooNoC (1M)
- 11:46, 3 November 2023 (diff | hist) . . (+532) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 14:46, 24 October 2023 (diff | hist) . . (+2) . . Routing 1000s of wires in Network-on-Chips (1-2S/M) (→Project)
- 14:45, 24 October 2023 (diff | hist) . . (+3,412) . . N Routing 1000s of wires in Network-on-Chips (1-2S/M) (Created page with "<!-- Backend explorations for Network-on-Chips (1-2S/M) --> Category:Digital Category:Network-on-Chip Category:Interconnect Category:Backend Category:2023...")
- 13:29, 24 October 2023 (diff | hist) . . (+3) . . Network-on-Chip for coherent and non-coherent traffic (M) (current)
- 13:27, 24 October 2023 (diff | hist) . . (+3) . . Network-off-Chip (M) (current)
- 13:27, 24 October 2023 (diff | hist) . . (+4,299) . . N Network-off-Chip (M) (Created page with "<!-- Network-off-Chip (M) --> Category:Digital Category:Network-on-Chip Category:Interconnect Category:2023 Category:Master Thesis Category:Fischeti [...")
- 13:18, 24 October 2023 (diff | hist) . . (+2,610) . . N Network-on-Chip for coherent and non-coherent traffic (M) (Created page with "<!-- Network-on-Chip for coherent and non-coherent traffic (M) --> Category:Digital Category:Network-on-Chip Category:Interconnect Category:2023 Category:Ma...")
- 12:44, 24 October 2023 (diff | hist) . . (+87) . . User:Fischeti
- 13:44, 23 October 2023 (diff | hist) . . (-4) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (current)
- 13:43, 23 October 2023 (diff | hist) . . (-4) . . AXI-based Network on Chip (NoC) system (current)
- 13:36, 8 March 2023 (diff | hist) . . (+44) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- 13:35, 8 March 2023 (diff | hist) . . (+201) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- 13:30, 8 March 2023 (diff | hist) . . (-2) . . Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (current)
- 13:30, 8 March 2023 (diff | hist) . . (-2) . . Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- 17:21, 20 February 2023 (diff | hist) . . (0) . . m Energy Efficient AXI Interface to Serial Link Physical Layer (Fischeti moved page Energy Efficient AXI Inteface to Serial Link Physical Layer to Energy Efficient AXI Interface to Serial Link Physical Layer: Typo) (current)
- 17:21, 20 February 2023 (diff | hist) . . (+74) . . N Energy Efficient AXI Inteface to Serial Link Physical Layer (Fischeti moved page Energy Efficient AXI Inteface to Serial Link Physical Layer to Energy Efficient AXI Interface to Serial Link Physical Layer: Typo) (current)
- 17:20, 20 February 2023 (diff | hist) . . (+21) . . Energy Efficient AXI Interface to Serial Link Physical Layer
- 17:18, 20 February 2023 (diff | hist) . . (+30) . . Energy Efficient AXI Interface to Serial Link Physical Layer
- 10:31, 2 November 2022 (diff | hist) . . (+1,829) . . N AXI-based Network on Chip (NoC) system (Created page with "<!-- AXI-based Network on Chip (NoC) system --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:Interconnect Categor...")
- 09:13, 2 November 2022 (diff | hist) . . (-176) . . m Flexfloat DL Training Framework (current)
- 09:04, 2 November 2022 (diff | hist) . . (+2) . . m Flexfloat DL Training Framework
- 09:03, 2 November 2022 (diff | hist) . . (+24) . . m Flexfloat DL Training Framework
- 08:59, 2 November 2022 (diff | hist) . . (+5) . . m Flexfloat DL Training Framework
- 08:57, 2 November 2022 (diff | hist) . . (+146) . . m Flexfloat DL Training Framework
- 08:55, 2 November 2022 (diff | hist) . . (-2) . . m Flexfloat DL Training Framework
- 08:54, 2 November 2022 (diff | hist) . . (+2) . . m User:Fischeti (→Projects In Progress)
- 08:54, 2 November 2022 (diff | hist) . . (+1) . . m User:Fischeti
- 08:53, 2 November 2022 (diff | hist) . . (+2) . . m Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- 08:51, 2 November 2022 (diff | hist) . . (+2) . . m Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- 08:49, 17 August 2022 (diff | hist) . . (-2) . . m A Unified Compute Kernel Library for Snitch (1-2S) (current)
- 08:47, 17 August 2022 (diff | hist) . . (0) . . m A Unified Compute Kernel Library for Snitch (1-2S)
- 08:46, 17 August 2022 (diff | hist) . . (+249) . . User:Fischeti
- 08:45, 17 August 2022 (diff | hist) . . (+251) . . m User:Fischeti (→Available Projects)
- 08:44, 17 August 2022 (diff | hist) . . (+2) . . m Flexfloat DL Training Framework
- 08:43, 17 August 2022 (diff | hist) . . (+2) . . m Flexfloat DL Training Framework (→Status: Available)
- 08:35, 17 August 2022 (diff | hist) . . (+2,152) . . N Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (Created page with "<!-- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (1S) --> Category:Digital Category:High Performance SoCs [[Category:Computer Architecture]...")
- 10:03, 12 August 2022 (diff | hist) . . (+251) . . m High Performance SoCs (→Who are we)
- 17:18, 19 November 2021 (diff | hist) . . (+1,213) . . N User:Fischeti (Created page with "thumb|right|280px == Tim Fischer == I received my Bachelor's degree in Information Technology and Electrical Engineering from Swiss Federal Institut...")
- 17:02, 19 November 2021 (diff | hist) . . (+250) . . m Deep Learning Projects (→Hardware Acceleration of DNNs and QNNs)
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