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Event-Driven Convolutional Neural Network Modular Accelerator

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Revision as of 10:58, 18 November 2019 by Adimauro (talk | contribs) (Introduction)
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In the last 10 years, Artificial Neural Networks (ANN) revolutionized many scientific fields by solving very difficult practical problems. Convolutional Neural Networks (CNN) is a very popular approach which allowed to reach state of the art accuracies in many different machine learning tasks, featuring a reasonably low memory footprint. For this reason, CNN are nowadays decently served by specialized CPU and GPU architectures, reaching very high energy efficiency per inference, and being deployed also to embedded devices for edge computing. In the last years, a new categories of efficient sensors is meeting a growing interest; ULP event-based cameras and audio sensors belong to this category. To efficiently exploit the nature of the data produced by such sensors, a paradigm shift in the way data are acquired and processed could be unavoidable. For this reason, research communities started focusing their interests on less conventional computing paradigms, such as event-driven computing. Spiking Neural Networks (SNN) represents a promising approach, and seems to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many edge applications in terms of energy consumption, thereby battery lifetime.

Project description

The student is required to:

Status: Available

Supervision: Alfio Di Mauro


Luca Benini

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Required Skills

To work on this project, you will need:

  • to have prior knowedge of analog circuit design

Other skills that you might find useful include:

  • familiarity with a scripting language
  • to be strongly motivated for a super-cool project

Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.


  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [2]
  • The IIS/DZ coding guidelines [3]