Difference between revisions of "Integrating Hardware Accelerators into Snitch (1S)"
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Latest revision as of 00:58, 23 November 2021
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
The Snitch system  targets energy-efficient high-performance computing. It is built around the tiny RISC-V Snitch integer core, coupled with a large double-precision floating-point unit (FPU) optimized for high-performance. Additionally, Snitch features two custom instruction-set-architecture (ISA) extensions, stream semantic registers (SSRs)  and the floating-point repetition (FREP) hardware loop, which allows the system to achieve FPU utilization above 90%.
With the slowdown of Moore's law, increased functionality and/or lower costs are achieved through domain specialization and heterogeneity. This led to an increased interest in domain-specific accelerators, which provide higher energy efficiency at a lower area cost.
HWPEs  are hardware accelerators that share the memory with the general-purposed cores and that are software-programmed by the cores. A plethora of HWPEs have been developed at our group, spanning from machine-learning engines  to accelerators targeting memory-bounded workloads . HWPEs have been historically integrated into the PULP cluster, but a Snitch-based system would greatly benefit by supporting these hardware modules.
The goal of this project is to implement the necessary architectural modifications to provide support for hardware processing engines (HWPE) in the Snitch cluster. Finally, some of the HWPEs developed at IIS can be used to evaluate the architectural improvements.
- Integrate the support for HWPEs in Snitch. This will require you to
- Investigate how the PULP cluster provide support for HWPE, in particular focusing on how the HWPEs connect to the memory and to the cores that program them
- Integrate support for HWPE in Snitch, implementing the necessary modifications
- Verify the functionality of your extensions.
- Evaluate your extensions by
- Adding one HWPE already developed at IIS to Snitch
- Determining the achieved speed-up for some target applications
- Determining the area and timing impact in synthesis
- Comparing them to the existing PULP cluster enhanced by the same HWPE.
- 15% Literature / architecture review
- 40% RTL implementation
- 15% Bare-metal C programming
- 30% Evaluation
- Strong interest in computer architecture
- Experience with digital design in SystemVerilog as taught in VLSI I
- Experience with ASIC implementation flow (synthesis) as taught in VLSI II