NeuroSoC RISC-V Component (M/1-2S)
From iis-projects
Contents
Overview
Status: Available
- Type: Master Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
Deployment of Artificial Intelligence (AI) at the edge presents many challenges as devices are resource-constrained in terms of memory and computation capacity, and must have a low power consumption profile while also being low cost. These constraints are becoming increasingly difficult to meet as advanced AI algorithms require Megabytes of storage and tens of billions of operations per second.
Hardware acceleration technologies based on neuromorphic and in-memory computing architectures have the potential to deliver a quantum leap in computational efficiency for AI applications.
The NeuroSoC project [1] will design and demonstrate an advanced Multiprocessor System-on-Chip based on Phase Change Memory (PCM) technology targeting a 100-fold improvement in computational efficiency, enabling an industry-proven path to bring AI to the edge.
The NeuroSoC advanced Multiprocessor System-on-Chip prototype will be developed in FD-SOI 28nm CMOS technology and will integrate an analog In-Memory Neural Processing Unit (IMNPU), a local digital processing subsystem, and functionally safe multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor implementation.
The In-Memory Neural Processing Unit (IMNPU) and associated digital peripheral circuitry will obviate the need to shuttle around millions of model parameters when running AI workloads such as deep neural networks (DNNs), greatly enhancing compute efficiency well beyond what purely digital solutions can achieve in traditional architecture. The architecture developed will be scalable, configurable, and parametric, in order to provide a hardware substrate that can target a variety of applications and can support a tradeoff between the capabilities, the size of the chip, the costs and the power consumption.
As one of the partners of this EU project, we will design a RISC-V component to support analog IMNPU units based on Snitch [2]. The current version of the Snitch cluster is available in [3]. The goal of this project is to modify and prepare the Snitch cluster for NeuroSoC.
Project
- Familiarize yourself with the Snitch cluster.
- Perform Design Space Exploration (DSE) to fit the Snitch cluster into the given area.
- Develop kernels to execute Transformer [4] workloads on the cluster.
- Integrate the cluster into the generic wrapper and extend the wrapper.
Character
- 20% Architecture review
- 20% RTL implementation
- 30% DSE
- 30% C programming
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I.
- Experience with C.
- Fundamental deep learning concepts.
