Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)

Overview

Status: Available

• Type: Master / Semester Thesis
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Thomas Benz: tbenz@iis.ee.ethz.ch
  • Paul Scheffler: paulsc@iis.ee.ethz.ch
  • Tim Fischer: fischeti@iis.ee.ethz.ch

Introduction

Today's systems are massively scaled out over huge spans of silicon or even over multiple dies. These systems usually no longer have a single memory controller (DDR5/HBM) but rather feature multiple and distributed memory controllers. This distribution of controllers makes the physical design and the interconnect of these systems easier but at the cost of a more complex data layout. To reach full throughput, the data must be distributed (e.g., interleaved) over multiple channels.

At IIS, we are working on a latency-tolerant DMA unit that supports transactions to multiple endpoints simultaneously. We recently created an initial draft support for memory interleaving directly within this DMA unit (the unit will do the interleaved accesses automatically and transparently to the user).

Project

In this project, you will take this draft of the DMA and finalize it. You will also evaluate the scalability of this approach by creating systems with a configurable amount of endpoints, DMA engines, and various on-chip network topologies (including off-chip die-to-die links).

Character

• 20% Getting familiar with the iDMA and Snitch
• 20% Finalizing the support for interleaved accesses
• 60% Evaluation of the approach on different configurations with different benchmarks

Prerequisites

• Interest in memory systems and computer architecture
• Experience with digital design in SystemVerilog as taught in VLSI I

References

[1] “A High-performance, Energy-efficient Modular DMA Engine Architecture” https://arxiv.org/abs/2305.05240