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- 17:58, 31 January 2021 (diff | hist) . . (+1,686) . . Manycore System on FPGA (M/S/G)
- 17:18, 31 January 2021 (diff | hist) . . (0) . . N File:Mempool logo.pdf (current)
- 17:12, 31 January 2021 (diff | hist) . . (-1) . . Transforming MemPool into a CGRA (M)
- 17:12, 31 January 2021 (diff | hist) . . (-2) . . Transforming MemPool into a CGRA (M)
- 17:10, 31 January 2021 (diff | hist) . . (+4) . . Transforming MemPool into a CGRA (M) (→Introduction)
- 17:10, 31 January 2021 (diff | hist) . . (0) . . N File:Mempool cgra.png (current)
- 17:08, 31 January 2021 (diff | hist) . . (+13,058) . . N Transforming MemPool into a CGRA (M) (Created page with "<!-- Transforming MemPool into a CGRA (M) --> = Overview = == Status: Available == * Type: Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sriedel...")
- 00:46, 31 January 2021 (diff | hist) . . (+6,925) . . N Manycore System on FPGA (M/S/G) (Created page with "<!-- Manycore System on FPGA --> = Overview = == Status: Available == * Type: Bachelor/Semester/Master Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** :User:Sri...")
- 19:19, 29 January 2021 (diff | hist) . . (-18) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (current)
- 19:16, 29 January 2021 (diff | hist) . . (-18) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 19:15, 29 January 2021 (diff | hist) . . (0) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 19:13, 29 January 2021 (diff | hist) . . (-1) . . ASIC Design Projects (→How does it work) (current)
- 19:12, 29 January 2021 (diff | hist) . . (+18) . . VLSI Implementation of a 5G Ciphering Accelerator
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . Event-Driven Convolutional Neural Network Modular Accelerator (→Links) (current)
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . Spiking Neural Network for Autonomous Navigation (→Links) (current)
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (→Links) (current)
- 19:10, 29 January 2021 (diff | hist) . . (+18) . . Level Crossing ADC For a Many Channels Neural Recording Interface (→Links) (current)
- 19:08, 29 January 2021 (diff | hist) . . (+18) . . Resilient Brain-Inspired Hyperdimensional Computing Architectures (current)
- 19:06, 29 January 2021 (diff | hist) . . (+76) . . ASIC Design Projects (→Newly available ASIC design projects from our group)
- 19:05, 29 January 2021 (diff | hist) . . (+1) . . Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (current)
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