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Showing below up to 20 results in range #101 to #120.

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101. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (14 revisions)
102. Finite Element Simulations of Transistors for Quantum Computing‏‎ (14 revisions)
103. High-speed Scene Labeling on FPGA‏‎ (14 revisions)
104. PULP in space - Fault Tolerant PULP System for Critical Space Applications‏‎ (14 revisions)
105. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (13 revisions)
106. Efficient collective communications in FlooNoC (1M)‏‎ (13 revisions)
107. Deep Learning for Brain-Computer Interface‏‎ (13 revisions)
108. On-Board Software for PULP on a Satellite‏‎ (13 revisions)
109. Neural Recording Interface and Signal Processing‏‎ (13 revisions)
110. CLIC for the CVA6‏‎ (13 revisions)
111. StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC‏‎ (13 revisions)
112. Level Crossing ADC For a Many Channels Neural Recording Interface‏‎ (13 revisions)
113. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT‏‎ (13 revisions)
114. Towards global Brain-Computer Interfaces‏‎ (13 revisions)
115. Integrated silicon photonic structures‏‎ (13 revisions)
116. LAPACK/BLAS for FPGA‏‎ (13 revisions)
117. Shared Correlation Accelerator for an RF SoC‏‎ (13 revisions)
118. GUI-developement for an action-cam-based eye tracking device‏‎ (13 revisions)
119. Turbo Equalization for Cellular IoT‏‎ (13 revisions)
120. On-chip clock synthesizer design and porting‏‎ (13 revisions)

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