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Showing below up to 20 results in range #51 to #70.

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51. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration‏‎ (20 revisions)
52. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA‏‎ (20 revisions)
53. Accelerator for Boosted Binary Features‏‎ (20 revisions)
54. Accelerator for Spatio-Temporal Video Filtering‏‎ (20 revisions)
55. FFT-based Convolutional Network Accelerator‏‎ (19 revisions)
56. Wireless Communication Systems for the IoT‏‎ (19 revisions)
57. Trace Debugger for custom RISC-V Core‏‎ (19 revisions)
58. PULP’s CLIC extensions for fast interrupt handling‏‎ (19 revisions)
59. 4th Generation Synchronization‏‎ (19 revisions)
60. VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE‏‎ (18 revisions)
61. Improving Scene Labeling with Hyperspectral Data‏‎ (18 revisions)
62. Flexfloat DL Training Framework‏‎ (18 revisions)
63. David J. Mack‏‎ (18 revisions)
64. Mapping Networks on Reconfigurable Binary Engine Accelerator‏‎ (18 revisions)
65. ASIC Implementation of High-Throughput Next Generation Turbo Decoders‏‎ (18 revisions)
66. Baseband Meets CPU‏‎ (17 revisions)
67. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs‏‎ (17 revisions)
68. Energy Efficient AXI Interface to Serial Link Physical Layer‏‎ (17 revisions)
69. Fast Accelerator Context Switch for PULP‏‎ (17 revisions)
70. Streaming Integer Extensions for Snitch (M)‏‎ (17 revisions - redirect page)

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