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• Energy Efficient Autonomous UAVs
  ...al class of devices used for such sophisticated algorithms are multi-cores high-end CPUs and embedded heterogeneous systems featuring powerful CPUs coupled Nowadays is well known how UAVs with high-level autonomous navigation capabilities are a hot topic both in industry a
  14 KB (2,077 words) - 15:02, 13 June 2022
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...e only at the end of 20th century, but it requires the development of high performance electronic devices. The research on the development of these electronic dev ...in significant experience with signal processing in the context of quantum computing experiments and FPGA hardware implementations
  5 KB (599 words) - 09:03, 21 December 2017
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
  ...d memory has doubled only every 30 months, becoming the bottleneck of high performance computers. ...n the optical domain can bypass those issues, allowing power efficient and high transmission rates.
  3 KB (382 words) - 11:44, 20 August 2021
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
  ..., the data streams that reflect the underlying neuron activity can present high spatial correlation among neighboring channels. This poses new challenges r * Evaluate Power/Performance/Area of the proposed implementation.
  5 KB (741 words) - 10:05, 18 November 2019
• Wireless Sensing With Long Range Comminication (LoRa)
  ...ce since low power microprocessors are weak in terms of computation power. High computation microprocessor are power hungry though. For these reasons, mult ...cation (simulations), measuring power-consumption, and assessing detection performance in lab. conditions
  5 KB (744 words) - 15:37, 10 November 2020
• AMZ Driverless Competition Embedded Systems Projects
  ...competition we started our second season willing to improve robustness and performance even further. We hope to be faster than a human driver in the coming years. ...cameras and an IMU allowing running visual inertial algorithms in the main computing system. In addition, some image processing should be done at this system to
  6 KB (895 words) - 16:27, 30 October 2020
• IBM Research
  ...n architecture, huge amounts of data need to be shuttled back and forth at high speeds, a task at which this architecture is inefficient. ...omputing paradigms from in-memory computing to brain-inspired neuromorphic computing. Our research spans from devices and architectures to algorithms and applic
  9 KB (1,330 words) - 15:20, 15 March 2024
• Finite Element Simulations of Transistors for Quantum Computing
  computing. The existing C++ code at IIS that solves this quantum transport problem is The idea of quantum computing is to associate a bit to a two-state quantum phenomenon (a “qu-bit”), s
  3 KB (432 words) - 14:14, 23 June 2021
• NVDLA meets PULP
  [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] in terms of performance, area, and power consumption. This includes getting familiar with NVDLA, un
  6 KB (799 words) - 13:42, 10 November 2020
• Heroino: Design of the next CORE-V Microcontroller
  ***Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32. ...s]] [[Category:Master Thesis]] [[Category:Hot]][[Category:High Performance Computing]][[Category:FPGA & Digital ASIC Design]][[Category:Embedded systems]][[Cate
  9 KB (1,314 words) - 00:01, 7 February 2021
• Manycore System on FPGA (M/S/G)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core syste
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...erators are not limited to the high-performance sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be per ==General-Purpose Computing==
  7 KB (917 words) - 17:04, 24 November 2023
• Finite element modeling of electrochemical random access memory
  ...of finite element modeling of electrochemical devices for analog computing. The work will be carried out in the Science & Technology Department at ...RAM operation and the influence of materialspropertiesand geometry on performance metrics requires a detailed multiphysics model
  4 KB (515 words) - 17:06, 16 September 2021
• Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  ..., which are 3D components that can be approximated as 2D slices, where the high dimension can be High Performance Computing is advantageous but not necessary.
  2 KB (327 words) - 17:06, 16 September 2021
• Event-Driven Convolutional Neural Network Modular Accelerator
  ...ed approaches seem to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many ed ...igurable in the type of neuron model to use, and in the number of physical computing engines instantiated. The accelerator operations are orchestrated by an RIS
  4 KB (651 words) - 19:10, 29 January 2021
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
  [[Category:Herschmi]][[Category:Event-Driven Computing]] ...your goal would be to improve algorithms, and implementations based on HD computing
  2 KB (308 words) - 20:12, 9 February 2020
• Spiking Neural Network for Autonomous Navigation
  ...pproach, and seems to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many ed 1. Study the SNN computing paradigm, and select a population of SNN candidate for the target task
  4 KB (644 words) - 19:10, 29 January 2021
• Semi-Custom Digital VLSI for Processing-in-Memory
  ...eless communication, where massive amounts of data need to be processed at high rates. [[Category:Event-Driven Computing]]
  7 KB (882 words) - 14:33, 28 July 2021
• Hyper-Dimensional Computing Based Predictive Maintenance
  Hyperdimensional computing (HDC) is an energy-efficient alternative to ...design the classification schemes using the primitives of hyperdimensional computing. In a second step, the algorithm should be tuned to be portable to an ultra
  5 KB (759 words) - 09:18, 16 September 2021
• Accurate deep learning inference using computational memory
  ...ty limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated. ...nts on phase-change memory chips comprising more than 1 million devices to high-level algorithmic development in a deep learning framework such as TensorFl
  5 KB (628 words) - 12:51, 17 April 2020
• Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  ...ion of implantable multielectrode-arrays (MEAs) to record brain signals at high spatio-temporal resolution. Data processing is needed to decode useful info ...omputing with numbers. HDC has proven to be promising for energy-efficient computing applied to biosignal classification [2].
  5 KB (619 words) - 19:58, 10 March 2024
• High Performance SoCs
  ==High-Performance Systems-on-Chip== ...n ever-increasing amount of '''parallel floating-point performance''' from computing systems. Increasingly, such applications must scale across a wide range of
  11 KB (1,337 words) - 10:54, 25 January 2024
• Energy Efficient SoCs
  ...SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators.
  3 KB (339 words) - 15:59, 1 November 2023
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core syste ...at 500MHz, and the L1 memory can be accessed by any of the cores through a high-throughput interconnection network with a round-trip latency of at most fiv
  8 KB (1,196 words) - 10:41, 6 July 2021
• Practical Reconfigurable Intelligent Surfaces (RIS)
  ...research for fifth-generation (5G) wireless systems and beyond, providing high data rates for all users was one of the key requirements. From now on, the ...e desired signal power and mitigate interference, improving the system’s performance, without the need of extra APs [4].
  8 KB (1,011 words) - 12:25, 16 November 2023
• Hypervisor Extension for Ariane (M)
  [[Category:High Performance SoCs]] ...ing systems (OSes) – a common technique used in secure systems and cloud computing to allow running untrusted OSes or multiple OSes in parallel.
  3 KB (391 words) - 08:49, 21 June 2022
• Matheus Cavalcante
  * High-Performance Computing
  890 bytes (104 words) - 18:33, 8 December 2020
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  [[Category:High Performance SoCs]] Much of our recent work on high-performance computing systems at IIS uses the ''Snitch'' cluster [[#ref-snitch|[3]]]. Thi
  11 KB (1,602 words) - 15:19, 9 July 2021
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  [[Category:High Performance SoCs]] ...lerator interface, allowing it to be paired with a powerful FPU to achieve high FPU utilizations and compute-over-control ratio.
  8 KB (1,220 words) - 15:18, 9 July 2021
• LLVM and DaCe for Snitch (1-2S)
  [[Category:High Performance SoCs]] ...system [[#ref-zaruba2020snitch|[1]]] targets energy-efficient high-performance systems. It is built around the minimal RISC-V Snitch core, only 15 kGE in
  11 KB (1,519 words) - 15:20, 9 July 2021
• Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  ...itional, high-resolution cameras. The student will use a cutting-edge high-performance embedded GPU to acquire data from these devices and run sensor-fusion based ...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
  2 KB (349 words) - 15:53, 11 October 2021
• Graph neural networks for epileptic seizure detection
  ...ning graphs with convolutional networks (GCNs), achieving state-of-the-art performance in public datasets [13].[14] proposed a temporal GCN to tackle the task of 1 - Development in a high-level programming language (python) of graph neural networks and/or convolu
  10 KB (1,306 words) - 19:58, 10 March 2024
• Huawei Research
  ===About the Huawei Future Computing Laboratory=== ...research laboratory focused on fundamental research in the area of future computing systems (new hardware, new software, new algorithms).
  6 KB (799 words) - 11:11, 1 August 2022
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
  ...t al., “Real-time brain-machine interface in non-human primates achieves high-velocity prosthetic finger movements using a shallow feedforward neural net
  5 KB (662 words) - 20:05, 10 March 2024
• Fast Simulation of Manycore Systems (1S)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of manycore system
  10 KB (1,434 words) - 17:20, 2 August 2021
• Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  ...f time-encoded SNNs to high-level system simulations in a high-performance computing framework. It also involves interactions with several researchers across IB ...or level and/or digital design with VHDL). Prior knowledge of neuromorphic computing concepts is a bonus but not necessary.
  3 KB (360 words) - 10:54, 31 August 2021
• Universal Stream Semantic Registers for Snitch (1S)
  [[Category:High Performance SoCs]] ...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
  3 KB (425 words) - 17:32, 17 November 2021
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  [[Category:High Performance SoCs]] ...e handling such streams in hardware. This frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also ''de
  4 KB (557 words) - 16:14, 6 November 2022
• Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  ...cision network to an appropriate representation and apply to it a suitable computing paradigm. ...gher precision. Our goal is therefore to keep this overhead of the sparse, high-precision part of the layer as small as possible and reach an optimal trade
  3 KB (497 words) - 22:15, 23 November 2022
• Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  ...s. However, the deployed networks have so far all been run at a relatively high numerical precision of 8 bits. ...er a simulation or the physical Kraken chip - see references) and evaluate performance compared to the 8-bit baseline
  8 KB (1,101 words) - 20:04, 10 March 2024
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  [[Category:High Performance SoCs]] ...hardware, which brings many benefits: it frees processors from explicitly computing addresses and issuing requests, increasing compute throughput. It also deco
  3 KB (431 words) - 16:13, 6 November 2022
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  ...ss communication, in which massive amounts of data need to be processed at high rates. [[Category:Event-Driven Computing]]
  7 KB (933 words) - 19:29, 21 November 2021
• Integration Of A Smart Vision System
  ...activity in their field of view, they send an alarm to a centralized high-performance vision platform, which is able to pan, tilt and zoom its field of view to t ...egory:Master Thesis]] [[Category:Bachelor Thesis]] [[Category:Event-Driven Computing]] [[Category:Hot]]
  3 KB (433 words) - 15:36, 4 August 2022
• Integrating Hardware Accelerators into Snitch (1S)
  ...with a large double-precision floating-point unit (FPU) optimized for high-performance. Additionally, Snitch features two custom instruction-set-architecture (ISA
  4 KB (567 words) - 13:57, 7 September 2022
• Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  [[Category:High Performance SoCs]] On the other hand, modern computing systems feature a number of ''performance counters'', i.e. hardware registers tracking carefully selected countable e
  5 KB (688 words) - 13:51, 27 October 2022
• Non-blocking Algorithms in Real-Time Operating Systems
  ...hardware and provide features such as efficient interrupt nesting to allow high priority interrupts to get the highest attention. On the software-level you Measure the performance impact, interrupt latency and jitter.
  4 KB (508 words) - 18:59, 10 January 2022
• Implementing DSP Instructions in Banshee (1S)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of manycore system
  10 KB (1,428 words) - 13:31, 27 October 2022
• SCMI Support for Power Controller Subsystem
  Today’s High Performance Computing (HPC) systems are complex architectures requiring on-chip dedicated HW reso ...explore.ieee.org/document/8065010 Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster]
  3 KB (467 words) - 13:55, 12 October 2022
• Serverless Benchmarks on RISC-V (M)
  [[Category:High Performance SoCs]] ...ior of these microservices/functions has been shown to have very different performance characteristics from traditional monolithic applications. For example, a sh
  6 KB (905 words) - 21:41, 6 December 2021
• Enhancing our DMA Engine with Fault Tolerance
  At IIS we are developing a modular and extensible high-performance direct memory access (DMA) engine. This DMA is integrated into a variety of ...le to runtime faults (SEUs), especially when deployed in environments with high levels of radiation, such as space. To combat this, a variety of redundancy
  2 KB (348 words) - 13:16, 24 October 2023

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