Search results
From iis-projects
Create the page "Processor" on this wiki! See also the search results found.
Page title matches
Page text matches
- ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]3 KB (377 words) - 10:25, 5 November 2019
- ...n are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is enough. A very simple 2-3stag ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]3 KB (384 words) - 17:24, 21 August 2019
- [[Category:Processor]]3 KB (450 words) - 11:43, 13 November 2018
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.5 KB (711 words) - 10:27, 5 November 2019
- [[Category:Processor]]3 KB (402 words) - 15:31, 13 April 2016
- [[Category:Processor]]3 KB (418 words) - 14:01, 13 November 2020
- ...ftware co-design in which part of the algorithm will be mapped onto a PULP processor while computational complex tasks are realized in dedicated hardware accele [[Category:Processor]]4 KB (555 words) - 16:36, 23 May 2018
- ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.2 KB (346 words) - 10:26, 5 November 2019
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.5 KB (712 words) - 17:57, 7 November 2017
- ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.6 KB (866 words) - 13:43, 29 November 2019
- ...sensors and one or two algorithms will be implemented directly in the PULP processor. One of main challenging goal of the project is bring these algorithm in an * programming the PULP processor for the specific application, otimize the code and carry out in-field testi4 KB (631 words) - 11:39, 21 July 2017
- ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp10 KB (1,357 words) - 16:25, 30 October 2020
- *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]3 KB (351 words) - 16:19, 27 February 2018
- ...m the ADC HW-FIFO to SW-FIFO at kernel-space and the real-time embedded co-processor ([http://beagleboard.org/pru PRU]) for post-processing of the data-stream. *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]3 KB (394 words) - 16:19, 27 February 2018
- *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]3 KB (440 words) - 16:15, 1 September 2017
- ...mic power controller algorithm is then needed to always configure the PULP processor in the most energy efficient point.3 KB (348 words) - 15:31, 13 September 2016
- ...ps (SoCs) often consist of various independent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking3 KB (389 words) - 11:20, 14 September 2016
- while the DBB processing can be done in a CPU, a Digital Signal Processor (DSP), an Appli- Open-RISC processor. The processor can be used to control the baseband blocks as well as to6 KB (900 words) - 16:58, 7 May 2018
- ...ystems Laboratory (IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-9 KB (1,427 words) - 18:36, 5 September 2019
- [[Category:Processor]]3 KB (392 words) - 14:17, 5 April 2022
- ...ger part of the affected digital baseband processing is mapped to a RISC-V processor, most of the work throughout the project requires embedded C coding, with s [[Category:Processor]]3 KB (462 words) - 13:54, 13 November 2020
- [[Category:Processor]]4 KB (467 words) - 13:38, 10 November 2020
- ...-power devices such as the PULP chips we develop at IIS. However, a vector processor shares many similarities with custom-designed HW accelerators that we have [[Category:Processor]]6 KB (916 words) - 15:50, 7 December 2018
- [[Category:Processor]]4 KB (546 words) - 11:33, 17 April 2020
- [[Category:Processor]]3 KB (372 words) - 20:22, 1 April 2019
- ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an [[Category:Processor]]3 KB (401 words) - 19:08, 29 January 2021
- ...it should not have any impact on the maximum achievable clock speed of the processor. Another challenge in designing a trace debugger is the fact that on-chip R * Basic knowledge of computer architecture/processor design as thought in the Energy-Efficient Parallel Computing Systems for Da5 KB (729 words) - 11:27, 11 December 2018
- [[Category:Processor]]3 KB (366 words) - 15:39, 10 November 2020
- architectures, where a powerful host processor is coupled to massively pushing for an architectural model where the host processor and the6 KB (865 words) - 12:16, 17 November 2017
- [[Category:Processor]]3 KB (409 words) - 13:58, 9 November 2017
- ...ea footprint. One way to reduce the area is the sharing of memory with the processor cluster. The final design can either be mapped to an FPGA, or an ASIC.3 KB (427 words) - 09:37, 14 September 2018
- [[Category:Processor]]4 KB (460 words) - 21:42, 30 January 2018
- ...ront ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip (RF-SoC) is mandatory to achieve minimal manufact3 KB (344 words) - 01:45, 10 February 2021
- [[Category:Processor]]3 KB (393 words) - 13:53, 13 November 2020
- ...n a general purpose microcontroller platform and on our own PULP multicore processor platforms. But as applications and research is changing fast, these impleme3 KB (317 words) - 14:40, 14 April 2021
- HERO combines an ARM Cortex-A host processor with a scalable, configurable, and extensible FPGA implementation of a prog3 KB (421 words) - 18:41, 28 October 2020
- ...e-core microcontrollers (i.e. Arm-Cortex-M family) or MultiCore (i.e. PULP Processor designed in IIS)5 KB (625 words) - 16:59, 10 November 2020
- ...sy reconfigurability of the oscillator with an external microcontroller or processor, while having outputs based on the I2S protocol that directly connect with [[Category:Processor]]5 KB (621 words) - 18:09, 9 October 2022
- [[Category:Processor]]5 KB (549 words) - 12:35, 28 November 2022
- ==Extremely Resilient HD Processor== ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an10 KB (1,341 words) - 10:46, 25 April 2018
- [[Category:Processor]]3 KB (354 words) - 16:06, 6 May 2019
- [[Category:Processor]]5 KB (599 words) - 09:03, 21 December 2017
- [[Category:Processor]]3 KB (329 words) - 11:43, 20 August 2021
- ...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface4 KB (518 words) - 11:40, 2 February 2018
- ...e exploring deep integration of analog precision circuits with the digital processor of the PULP family, both workforce and expertise converge on the VivoSoC pr2 KB (327 words) - 19:55, 22 February 2018
- [[Category:Processor]]4 KB (597 words) - 19:15, 9 March 2020
- [[Category:Processor]]4 KB (661 words) - 08:38, 20 January 2021
- [[Category:Processor]]3 KB (381 words) - 14:17, 28 January 2023
- ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor2 KB (311 words) - 12:02, 5 December 2018
- [[Category:Processor]]4 KB (566 words) - 15:50, 9 February 2021