Taping a Safer Silicon Implementation of Snitch (M/2-3S)
From iis-projects
Contents
Overview
Status: Available
- Type: ASIC Master / Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
We recently started testing Occamy, our massive 434-core general-purpose compute accelerator based on the Snitch architecture. We can successfully run code on the two Linux-capable cores and on the 432 Snitch cores. However, we have identified some dangerous design practices that could have ended Occamy if we had not had any failsafe mechanisms in place. We want to understand these issues in more detail and fix them to make further tapeouts safer.
Project
In this project, you will certainly investigate and implement/improve the following design aspects:
- Simplified cluster-local and bypassable bootrom
- Safer implementation of WFI
- Making the Snitch core debuggable with GDB
- Remove all non-resettable flip-flops
- Pushing the parameterization of the cluster to the limit: Is a single-core cluster possible?
- Improving on of our FLL IPs
- Adding features that ease debugging on the ASIC tester, e.g., creating an FLL-observation unit.
You will then verify these changes on an FPGA or in a post-layout simulation before taping a Snitch system with your changes. During your project, you will be able to run real workloads on Occamy to understand better the issues mentioned above.
Character
- 20% Study Snitch, evaluate the issues on Occamy
- 20% Design, implementation, and verification of your changes
- 60% Tapeout a Snitch-based system
Prerequisites
- Interest in computer architecture
- Experience with digital design in SystemVerilog as taught in VLSI I
- Visited/visiting VLSI II or an equivalent lecture
