Difference between revisions of "User:Prasadar"
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==Interests== | ==Interests== | ||
| − | + | I am fascinated towards bringing AR/VR experience to the edge. I work on implementing algorithm for Visual applications, map them to the hardware, hardware design to deploy the relevant workloads on FPGA/ASIC, architecture exploration using system simulation. To summarize my interests in a few keywords | |
| − | * | + | * Deep Neural Networks |
* FPGA & Digital ASIC Design | * FPGA & Digital ASIC Design | ||
| + | * Visual Algorithms tailored for AR/VR | ||
| + | * System Simulation | ||
| + | * Hardware Acceleration of DNN | ||
==Contact Information== | ==Contact Information== | ||
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* '''e-mail''': [mailto:prasadar@iis.ee.ethz.ch prasadar@iis.ee.ethz.ch] | * '''e-mail''': [mailto:prasadar@iis.ee.ethz.ch prasadar@iis.ee.ethz.ch] | ||
* '''www''': [https://iis.ee.ethz.ch/people/person-detail.MjUzMTc0.TGlzdC8zOTg3LDk5MDE4ODk4MA==.html Arpan Suravi Prasad (ETH page)] | * '''www''': [https://iis.ee.ethz.ch/people/person-detail.MjUzMTc0.TGlzdC8zOTg3LDk5MDE4ODk4MA==.html Arpan Suravi Prasad (ETH page)] | ||
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==Available Projects== | ==Available Projects== | ||
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category = Prasadar | category = Prasadar | ||
</DynamicPageList> | </DynamicPageList> | ||
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| + | == Projects in Progress== | ||
| + | <DynamicPageList> | ||
| + | supresserrors = true | ||
| + | category = In progress | ||
| + | category = Prasadar | ||
| + | </DynamicPageList> | ||
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[[Category: Supervisors]] | [[Category: Supervisors]] | ||
Latest revision as of 16:59, 12 December 2023
Contents
Arpan Suravi Prasad
I received my M.Sc. degree in Electrical Engineering and Information Technology from the Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland in March 2021. After that, I started as a Ph.D. Student in the Digital Circuits and Systems Group of Prof. Dr. L. Benini.
Interests
I am fascinated towards bringing AR/VR experience to the edge. I work on implementing algorithm for Visual applications, map them to the hardware, hardware design to deploy the relevant workloads on FPGA/ASIC, architecture exploration using system simulation. To summarize my interests in a few keywords
- Deep Neural Networks
- FPGA & Digital ASIC Design
- Visual Algorithms tailored for AR/VR
- System Simulation
- Hardware Acceleration of DNN
Contact Information
- Office: ETZ J89
- telephone: (+41 44 63) 244 91
- e-mail: prasadar@iis.ee.ethz.ch
- www: Arpan Suravi Prasad (ETH page)
Available Projects
- Modeling FlooNoC in GVSoC (S/M)
- Realtime Gaze Tracking on Siracusa
- System Emulation for AR and VR devices
Projects in Progress
No pages meet these criteria.
