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- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1 Semester/Bachelor students6 KB (741 words) - 18:14, 21 July 2023
- <!-- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) -->1 KB (188 words) - 09:39, 3 November 2023
- : Looking for 1-2 Semester/Master students6 KB (820 words) - 12:13, 23 July 2023
- : Looking for 1 Semester/Bachelor students5 KB (644 words) - 18:18, 21 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1-2 Semester/Master students6 KB (735 words) - 12:12, 23 July 2023
- #Redirect [[A Snitch-based Compute Accelerator for HERO (M/1-2S)]]66 bytes (10 words) - 21:47, 10 November 2020
- <!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> ...pen-source Parallel Ultra-Low Power (PULP) platform [<nowiki/>[[#ref-pulp|1]]] , which provides a multicore cluster based on the open RISC-V instructio11 KB (1,617 words) - 23:59, 6 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]2 KB (333 words) - 20:05, 15 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]3 KB (386 words) - 20:06, 15 February 2021
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4 KB (617 words) - 10:19, 3 November 2023
- 1. Install MemPool and test it on different configurations ...RTL language (SystemVerilog or Verilog or VHDL). Having followed the VLSI 1 course is recommended.8 KB (1,196 words) - 10:41, 6 July 2021
- <!-- (1-2S): An RPC DRAM Implementation for Energy-Efficient ASICs --> .... These ''reduced pin count DDR'' (RPC DDR) [[[#ref-rpc_dram_website|1]]] memories only require a simple on-chip PHY and can operate with regular8 KB (1,214 words) - 15:18, 9 July 2021
- #Redirect [[A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)]]2 KB (365 words) - 20:03, 15 February 2021
- ...Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) --> ...Ariane cores, and die-to-die serial link. [[#ref-zaruba2020manticore|[1]]]]]11 KB (1,602 words) - 15:19, 9 July 2021
- Ara is working well, with a prototype achieving an operating frequency of 1 GHz in a modern technology. 1. Familiarize with the RISC-V Vector Extension and the Ara source code. (~26 KB (916 words) - 15:25, 9 July 2021
- <!-- (1-2S/B): A Snitch-Based SoC on iCE40 FPGAs --> With the iCE40 FPGA family, Lattice Semiconductor [[[#ref-fpga|1]]] provides FPGAs with the world’s smallest form factor, optimized for u8 KB (1,220 words) - 15:18, 9 July 2021
Page text matches
- * Consider about 1 slide per minute on average for your slides.1 KB (187 words) - 18:53, 22 March 2020
- : Looking for 1-2 Semester/Master students3 KB (409 words) - 10:52, 27 March 2014
- : Looking for 1-2 Semester/Master students4 KB (397 words) - 15:44, 14 February 2023
- ...ion methods including magnetic, electrostatic, and electrochemical effects[1,2,3], thus they can be better controlled for many applications. To better u2 KB (328 words) - 10:21, 14 February 2023
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''4 KB (444 words) - 12:43, 23 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1 Semester/Bachelor students6 KB (741 words) - 18:14, 21 July 2023
- ...bi equalizer. A high-level block diagram of the algorithm is shown in Fig. 1. In the ing is explained in more details in [1]. The preprocessing step is concluded with deciding over5 KB (684 words) - 10:43, 6 November 2017
- * Start with a 1-2 sentence summary of your project. (this can be repeated every week the sa IPC = 1).7 KB (1,133 words) - 07:08, 7 October 2023
- ...correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transcei : Looking for 1-2 Semester/Master students3 KB (382 words) - 20:00, 26 September 2017
- <!--: Looking for 1-2 Semester/Master students3 KB (392 words) - 12:33, 15 April 2016
- : Looking for 1-2 Semester/Master students3 KB (385 words) - 11:13, 14 April 2016
- : Looking for 1-2 Semester/Master students3 KB (508 words) - 11:12, 14 April 2016
- : Looking for 1-2 Semester/Master students2 KB (300 words) - 14:11, 13 March 2014
- : Looking for 1-2 Semester/Master students3 KB (492 words) - 12:34, 7 November 2017
- : Looking for 1-2 Semester/Master students3 KB (407 words) - 10:57, 5 November 2019
- : Looking for 1 Master student3 KB (429 words) - 09:42, 12 October 2017
- the OsmocomBB project [1] has implemented a relatively [1] OsmocomBB. http://bb.osmocom.org/trac/, April 2015.3 KB (421 words) - 10:40, 6 November 2017
- ...aseband Processing (DBB) from the [[RazorEDGE]] project on an ML605 board [1] and RF processing on the [[evalEDGE]] FMC module is available. A separate [1] [http://www.xilinx.com/ml605 Virtex-6 FPGA ML605 Evaluation Kit], June 2012 KB (273 words) - 11:30, 24 February 2017
- ...the 3GPP standard organization include enhancements to 2G and 4G networks [1] refereed to as EC-GSM-IoT and NB-IoT to enhance coverage by up to 20 dB an2 KB (277 words) - 17:59, 29 March 2017