User contributions
From iis-projects
- 16:35, 16 February 2024 diff hist -1 User:Colluca →Luca Colagrande
- 16:34, 16 February 2024 diff hist +34 User:Colluca →Luca Colagrande
- 12:43, 3 November 2023 diff hist 0 User:Colluca →Luca Colagrande
- 12:42, 3 November 2023 diff hist +7 User:Colluca →Luca Colagrande
- 12:42, 3 November 2023 diff hist +51 User:Colluca →Luca Colagrande
- 12:28, 3 November 2023 diff hist 0 Efficient collective communications in FlooNoC (1M) →Introduction
- 12:28, 3 November 2023 diff hist +6 Efficient collective communications in FlooNoC (1M) →Introduction
- 12:21, 3 November 2023 diff hist 0 Efficient collective communications in FlooNoC (1M) →Introduction
- 12:20, 3 November 2023 diff hist +108 N File:Floonoc paper fig4.png Physical implementation of FlooNoC connecting a mesh of compute tiles in GlobalFoundries’ 12 nm technology current
- 12:18, 3 November 2023 diff hist +59 Efficient collective communications in FlooNoC (1M) →Introduction
- 12:17, 3 November 2023 diff hist -74 Efficient collective communications in FlooNoC (1M) →Project description
- 12:13, 3 November 2023 diff hist +12 Efficient collective communications in FlooNoC (1M) →Project description
- 12:12, 3 November 2023 diff hist +5,693 N Efficient collective communications in FlooNoC (1M) Created page with "<!-- Efficient collective communications in FlooNoC (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis Category:H..."
- 11:21, 20 October 2023 diff hist +180 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:51, 17 October 2023 diff hist +138 Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 09:57, 17 October 2023 diff hist +107 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) →Stretch goals
- 09:57, 17 October 2023 diff hist +73 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) →Detailed task description
- 09:56, 17 October 2023 diff hist -67 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) →Stretch goals
- 11:37, 16 October 2023 diff hist +131 Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 15:12, 3 October 2023 diff hist -19 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 15:12, 3 October 2023 diff hist 0 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 15:11, 3 October 2023 diff hist +7 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 15:11, 3 October 2023 diff hist +21 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 15:10, 3 October 2023 diff hist +272 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 18:22, 29 September 2023 diff hist +2 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 18:21, 29 September 2023 diff hist +2 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) →Status: Available
- 18:21, 29 September 2023 diff hist +79 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 18:19, 29 September 2023 diff hist +2 Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 18:19, 29 September 2023 diff hist +83 Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 18:17, 29 September 2023 diff hist -2 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 18:16, 29 September 2023 diff hist +3 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Status: Reserved
- 13:46, 5 September 2023 diff hist +91 A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) →Status: Available
- 11:20, 5 September 2023 diff hist +4 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 11:20, 5 September 2023 diff hist +62 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 17:18, 4 September 2023 diff hist -19 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 17:18, 4 September 2023 diff hist +5,919 N Accelerating Matrix Multiplication on a 216-core MPSoC (1M) Created page with "<!-- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis Ca..."
- 16:24, 4 September 2023 diff hist +1 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) →Status: Available
- 16:24, 4 September 2023 diff hist +11 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 00:03, 10 August 2023 diff hist +6,677 N A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) Created page with "<!-- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Maste..."
- 00:03, 10 August 2023 diff hist +51 N File:Snitch block diagram.png A block diagram of the Snitch cluster architecture. current
- 15:53, 9 August 2023 diff hist +1 High Performance SoCs →Matteo Perotti
- 15:53, 9 August 2023 diff hist 0 High Performance SoCs →Luca Colagrande
- 15:52, 9 August 2023 diff hist 0 Matteo Perotti →Contact Information current
- 15:52, 9 August 2023 diff hist 0 User:Colluca →Contact
- 15:19, 12 May 2023 diff hist +12 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 15:18, 12 May 2023 diff hist +53 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 15:10, 12 May 2023 diff hist +2 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:09, 12 May 2023 diff hist -2 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Status: Available
- 15:09, 12 May 2023 diff hist +7 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →References
- 15:07, 12 May 2023 diff hist +32 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Stretch goals