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Showing below up to 50 results in range #401 to #450.
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- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers (11:08, 12 November 2020)
- Low-Resolution 5G Beamforming Codebook Design (11:37, 12 November 2020)
- Real-Time Optimization (13:57, 12 November 2020)
- Deep Unfolding of Iterative Optimization Algorithms (13:57, 12 November 2020)
- LightProbe - CNN-Based-Image-Reconstruction (20:46, 12 November 2020)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (20:47, 12 November 2020)
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) (20:48, 12 November 2020)
- Ultrasound High Speed Microbubble Tracking (20:49, 12 November 2020)
- LightProbe - Thermal-Power aware on-head Beamforming (20:50, 12 November 2020)
- LightProbe - Frontend Firmware and Control Side Channel (20:51, 12 November 2020)
- 3D Ultrasound Bubble Tracking (20:52, 12 November 2020)
- Satellite Internet of Things (13:53, 13 November 2020)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (13:54, 13 November 2020)
- Next Generation Channel Decoder (14:01, 13 November 2020)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (15:31, 16 November 2020)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (19:40, 16 November 2020)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (11:39, 30 November 2020)
- Smart Patch For Heath Care And Rehabilitation (16:24, 30 November 2020)
- Matheus Cavalcante (18:33, 8 December 2020)
- Improved Reacquisition for the 5G Cellular IoT (14:04, 11 January 2021)
- ASIC Design of a Gaussian Message Passing Processor (08:34, 20 January 2021)
- ASIC Design of a Sigma Point Processor (08:34, 20 January 2021)
- Hardware Accelerator for Model Predictive Controller (08:35, 20 January 2021)
- Fast Wakeup From Deep Sleep State (08:35, 20 January 2021)
- Compressed Sensing for Wireless Biosignal Monitoring (08:35, 20 January 2021)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (08:36, 20 January 2021)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (08:37, 20 January 2021)
- Extend the RI5CY core with priviledge extensions (08:38, 20 January 2021)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (08:42, 20 January 2021)
- MemPool on HERO (1S) (19:07, 20 January 2021)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (19:05, 29 January 2021)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (19:08, 29 January 2021)
- Level Crossing ADC For a Many Channels Neural Recording Interface (19:10, 29 January 2021)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (19:10, 29 January 2021)
- Spiking Neural Network for Autonomous Navigation (19:10, 29 January 2021)
- Event-Driven Convolutional Neural Network Modular Accelerator (19:10, 29 January 2021)
- ASIC Design Projects (19:13, 29 January 2021)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (19:19, 29 January 2021)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (23:59, 6 February 2021)
- Heroino: Design of the next CORE-V Microcontroller (00:01, 7 February 2021)
- VLSI Implementation of a 5G Ciphering Accelerator (10:05, 9 February 2021)
- OTDOA Positioning for LTE Cat-M (15:50, 9 February 2021)
- ASIC Development of 5G-NR LDPC Decoder (01:43, 10 February 2021)
- Wireless Communication Systems for the IoT (01:45, 10 February 2021)
- Software-Defined Paging in the Snitch Cluster (2-3S) (20:08, 15 February 2021)
- Event-Driven Vision on an embedded platform (08:41, 17 February 2021)
- Efficient TNN compression (08:41, 17 February 2021)
- Design and Evaluation of a Small Size Avalanche Beacon (10:02, 22 February 2021)
- ISA extensions in the Snitch Processor for Signal Processing (M) (00:08, 13 March 2021)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (15:40, 15 March 2021)
