Category:Digital
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Pages in category "Digital"
The following 200 pages are in this category, out of 617 total.
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- Android reliability governor
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASR-Waveformer
- Audio DAC Conversion Jitter Measurement System
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Automatic unplugging detection for Ultrasound probes
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Sensors for IoT
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- AXI-based Network on Chip (NoC) system
B
- Bandwidth Efficient NEureka
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
- User:Barandre
- Baseband Meets CPU
- Bateryless Heart Rate Monitoring
- Battery indifferent wearable Ultrasound
- BCI-controlled Drone
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benjamin Weber
- Big Data Analytics Benchmarks for Ara
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Biomedical Circuits, Systems, and Applications
- BirdGuard
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- User:Bjoernf
- BLISS - Battery-Less Identification System for Security
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
C
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- User:Cioflanc
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- CLIC for the CVA6
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing vs JPEG
- Compression of iEEG Data
- Compression of Ultrasound data on FPGA
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- CPS Software-Configurable State-Machine
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating a HDMI Video Interface for PULP
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cycle-Accurate Event-Based Simulation of Snitch Core
D
- Data Augmentation Techniques in Biosignal Classification
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Deep Learning for Brain-Computer Interface
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep neural networks for seizure detection
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Fused Multiply Add Floating Point Unit
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of a VLIW processor architecture based on RISC-V
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an LTE Module for the Internet of Things
- Design of combined Ultrasound and Electromyography systems
- Design of combined Ultrasound and PPG systems
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Designing a Power Management Unit for PULP SoCs
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Development of a Rockfall Sensor Node
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Development of statistics and contention monitoring unit for PULP
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Beamforming for Ultrasound Imaging
- Digital Transmitter for Mobile Communications
- DigitalUltrasoundHead
- DMA Streaming Co-processor
- User:Dpalossi
E
- Edge Computing for Long-Term Wearable Biomedical Systems
- EEG artifact detection for epilepsy monitoring
- EEG artifact detection with machine learning
- EEG earbud
- EEG-based drowsiness detection
- Efficient collective communications in FlooNoC (1M)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Search Design for Hyperdimensional Computing
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN compression
- Efficient TNN Inference on PULP Systems
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy Efficient Autonomous UAVs
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Neutral Multi Sensors Wearable Device
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating the RiscV Architecture
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring NAS spaces with C-BRED
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fabian Schuiki
- Fast Accelerator Context Switch for PULP
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fast Simulation of Manycore Systems (1S)
- Fast Wakeup From Deep Sleep State
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- User:Fischeti
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA mapping of RPC DRAM
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- Frank K. Gürkaynak
- Freedom from Interference in Heterogeneous COTS SoCs