Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
From iis-projects
Contents
Overview
Status: Reserved
- Type: Computer Architecture Master / Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
MemPool[1] is an example of the massively parallel SoCs built at IIS. It integrates 256 Snitch cores and 1MiB of shared-L1 memory. Despite its size, MemPool gives all cores low-latency access to the shared L1 memory, with a maximum latency of only five cycles when no contention occurs. This implements efficient communication among all cores, making MemPool suitable for various workload domains and easy to program.
Today, MemPool is a standalone cluster of accelerators with distributed memory, but it aims to be programmed by and for a Host subsystem
Cheshire[2], an open-source SoC from our group that features a 64-bit RISC-V core and various peripherals such as UART, SPI, I2C, VGA and more. It is intended as a pluggable host system that can be reused in Heterogeneous SoCs.
The goal of this work will be to build a RTL top level for a future SoC gathering a Cheshire host subsystem with a Mempool accelerator subsystem.
Project
This work will go through multiple of the steps required when proposing a new SoC. After a first architectural proposal, the student will build the top level of the future SoC using System Verilog and verify the communication between the Host and Accelerator subsystems.
Then, the student will adapt the existing FPGA flow of Cheshire to test the Linux boot on this new platform.
Finally, a Master thesis student will extend this work with one of the following points
- Extending the HERO runtime for Mempool and benchmark OpenMP [3] kernels on this platform
- Adapt previous synthesis and implementation flows to get an area estimation of the SoC in GF12
- Integrate a verified RISC-V compliant IOMMU [4] to simplify shared memory based communication between Mempool and Cheshire
Character
- 40% Architecture pre-study, RTL top level
- 20% Verification of the memory accesses among the chip
- 40% FPGA implementation and booting Linux
Master thesis:
After completing the three points above, an estimated 30% time of the thesis will be dedicated to one of the stretch goal defined in the Project section.
Prerequisites
- Good knowledge of computer architectures
- Proficient in System Verilog
- Proficient in C
- Willing to learn about Linux and Linux drivers
References
[1] https://github.com/pulp-platform/cheshire
[2] https://pulp-platform.org/docs/lugano2023/MemPool_05_06_23.pdf
