Difference between revisions of "Accelerator for Spatio-Temporal Video Filtering"
From iis-projects
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"[[Real-time View Synthesis using Image Domain Warping]]" and "[[A Multiview Synthesis Core in 65 nm CMOS]]". | "[[Real-time View Synthesis using Image Domain Warping]]" and "[[A Multiview Synthesis Core in 65 nm CMOS]]". | ||
| − | The goal of this project | + | The goal of this project is to look into an advanced saliency estimation |
algorithm, and to develop an efficient hardware architecture for it. Depending on | algorithm, and to develop an efficient hardware architecture for it. Depending on | ||
the progress, the implementation can also be prototyped on a FPGA. | the progress, the implementation can also be prototyped on a FPGA. | ||
Revision as of 17:29, 21 February 2014
Example for a saliency map (image copyright belongs to the [Blender Foundation]).
Contents
Short Description
Saliency estimation is an important building block in video processing applications. The goal of saliency estimation is to find visually important regions in the image, and this information can be used in further processing steps to adapt the video in a content-aware fashion. Examples for applications that use saliency estimates are "Real-time View Synthesis using Image Domain Warping" and "A Multiview Synthesis Core in 65 nm CMOS".
The goal of this project is to look into an advanced saliency estimation algorithm, and to develop an efficient hardware architecture for it. Depending on the progress, the implementation can also be prototyped on a FPGA.
Status: Available
- Scope: Semester or Master Thesis
- Looking for 1-2 Interested Students
- Supervisors: Frank Gürkaynak, Michael Schaffner
Prerequisites
- VLSI I
- Introductory course in computer vision (recommended)
- Interest in computer graphics / computer vision
- Matlab, VHDL and C++
Character
- 25% Theory & Literature Study
- 25% Matlab Evaluations
- 50% Hw Architecture & FPGA Implementation
Professor
Partners
Detailed Task Description
Goals
Practical Details
