Difference between revisions of "DMA Streaming Co-processor"
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==Short Description== | ==Short Description== | ||
Linear solvers can be used in many image and video processing applications, e.g. for optical-flow calculation or image domain warping (IDW). In a [http://www.disneyresearch.com/wp-content/uploads/DRAM-or-no-DRAM-Exploring-Linear-Solver-Architectures-for-Image-Domain-Warping-in-28-nm-CMOS-Paper.pdf recent publication] we estimated the area, throughput and power consumption for different solver implementations, and we would now like to verify some of these estimated results using post-layout simulations and ASIC measurements. Besides the verification of these results, we are interested in how well estimation methods at various levels (pre-RTL estimations, gate-level simulations, post-layout simulations) actually match with the measurements of a fabricated ASIC. | Linear solvers can be used in many image and video processing applications, e.g. for optical-flow calculation or image domain warping (IDW). In a [http://www.disneyresearch.com/wp-content/uploads/DRAM-or-no-DRAM-Exploring-Linear-Solver-Architectures-for-Image-Domain-Warping-in-28-nm-CMOS-Paper.pdf recent publication] we estimated the area, throughput and power consumption for different solver implementations, and we would now like to verify some of these estimated results using post-layout simulations and ASIC measurements. Besides the verification of these results, we are interested in how well estimation methods at various levels (pre-RTL estimations, gate-level simulations, post-layout simulations) actually match with the measurements of a fabricated ASIC. |
Revision as of 16:27, 13 May 2015
Contents
Short Description
Linear solvers can be used in many image and video processing applications, e.g. for optical-flow calculation or image domain warping (IDW). In a recent publication we estimated the area, throughput and power consumption for different solver implementations, and we would now like to verify some of these estimated results using post-layout simulations and ASIC measurements. Besides the verification of these results, we are interested in how well estimation methods at various levels (pre-RTL estimations, gate-level simulations, post-layout simulations) actually match with the measurements of a fabricated ASIC.
Status: Available
- Scope: Semester or Master Thesis
- Looking for 1-2 Interested Students
- Supervisors: Frank Gürkaynak, Michael Schaffner
Prerequisites
- VLSI I
- Basic Linear Algebra Course
- Matlab, VHDL and C++
Character
- 25% Theory & Literature Study
- 25% Evaluations
- 50% Hw Architecture & ASIC Implementation