Difference between revisions of "Energy Efficient AXI Interface to Serial Link Physical Layer"
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= Overview = | = Overview = | ||
| − | == Status: Available == | + | ===Status: Available=== |
| + | :Looking for master or semester thesis students | ||
| + | :Supervisor: | ||
| + | **[[:User:sarjmandpour | Sina Arjmandpour]]: [mailto:sarjmandpour@iis.ee.ethz.ch sarjmandpour@iis.ee.ethz.ch] | ||
| + | ** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch] | ||
| − | * | + | ===Prerequisites=== |
| − | * | + | * Experience with System Verilog or Verilog, VLSI 1 |
| + | * Experience with physical implementation, VLSI 2 | ||
| + | ===Character=== | ||
| + | * 20% System Integration | ||
| + | * 20% Verification | ||
| + | * 30% Low-level software and drivers | ||
| + | * 30% Backend implementation | ||
| − | == | + | ===Professor=== |
| + | *Prof. Dr. Luca Benini | ||
| + | *Prof. Dr. Taekwang Jang | ||
| − | + | === Reference=== | |
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| − | == | ||
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Revision as of 14:53, 13 February 2023
Contents
Overview
Status: Available
- Looking for master or semester thesis students
- Supervisor:
Prerequisites
- Experience with System Verilog or Verilog, VLSI 1
- Experience with physical implementation, VLSI 2
Character
- 20% System Integration
- 20% Verification
- 30% Low-level software and drivers
- 30% Backend implementation
Professor
- Prof. Dr. Luca Benini
- Prof. Dr. Taekwang Jang
