Difference between revisions of "Energy Efficient Serial Link"

Revision as of 14:53, 13 February 2023

@@ Line 11: / Line 11: @@
 </DynamicPageList>
-===Status: Available===
-:Looking for master or semester thesis students
-:Supervisor:
-**[[:User:sarjmandpour | Sina Arjmandpour]]: [mailto:sarjmandpour@iis.ee.ethz.ch sarjmandpour@iis.ee.ethz.ch]
-** [[:User:Fischeti | Tim Fischer]]: [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
-===Prerequisites===
-* Experience with System Verilog or Verilog, VLSI 1
-* Experience with physical implementation, VLSI 2
-===Character===
-* 20% System Integration
-* 20% Verification
-* 30% Low-level software and drivers
-* 30% Backend implementation
-===Professor===
-*Prof. Dr. Luca Benini
-*Prof. Dr. Taekwang Jang
-=== Reference===
 [[#top|↑ top]]

	Privacy policy About iis-projects Disclaimers
	Mozilla Cavendish Theme based on Cavendish style by Gabriel Wicke modified by DaSch for the Web Community Wiki github Projectpage – Report Bug – Skin-Version: 2.3.5