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Fast Wakeup From Deep Sleep State

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Short Description

Typical IoT power cycle
Architecture with reusable IPs highlighted

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power consumption. In such applications optimizing the wakeup energy consumption has a significant impact on the overall energy drawn from the battery. The goal of the project is to implement an hardware IP to enable fast save and restore of the status of the PULP multicore platform reusing as much as possible existing components. The project can be summarized as follows:

*Implement SW based save/restore
*Extend the current debug unit and make it memory mapped
*Control system DMA to save/restore L1 data memory
*Dump core state to memory via debug unit
*Validate the design and compare with SW solution
*Power estimation

Status: Available

Semester/Master Thesis
Supervision: Antonio Pullini (IIS)

Professor

Luca Benini

Character

20% Embedded programming
40% HW design
40% System validation

Requirements

Knowledge of C/C++ VHDL or Verilog HDL

Links

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