Difference between revisions of "Fault-Tolerant Floating-Point Units (M)"
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= Overview = | = Overview = | ||
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** [[:User:Lbertaccini | Luca Bertaccini]]: [mailto:lbertaccini@iis.ee.ethz.ch lbertaccini@iis.ee.ethz.ch] | ** [[:User:Lbertaccini | Luca Bertaccini]]: [mailto:lbertaccini@iis.ee.ethz.ch lbertaccini@iis.ee.ethz.ch] | ||
+ | ** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch] | ||
= Introduction = | = Introduction = |
Revision as of 12:13, 13 November 2023
Contents
Overview
Status: Available
- Type: Master Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
Fault-tolerant features are crucial in critical and hostile environments (automotive, space, …). The goal of this project is to enhance the FP unit (FPU) developed at IIS [1] with fault-tolerant features (such as redundancy schemes [2]).
Character
- 20% Literature / architecture review
- 40% RTL implementation
- 40% Evaluation
Prerequisites
- Strong interest in computer architecture
- Experience with digital design in SystemVerilog as taught in VLSI I
- Experience with ASIC implementation flow (synthesis) as taught in VLSI II