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Showing below up to 100 results in range #501 to #600.
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- On-Board Software for PULP on a Satellite
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- On-chip clock synthesizer design and porting
- On - Device Continual Learning for Seizure Detection on GAP9
- Online Learning of User Features (1S)
- OpenRISC SoC for Sensor Applications
- Open Power-On Chip Controller Study and Integration
- Optimal System Duty Cycling
- Optimal System Duty Cycling for a Mobile Health Platform
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Outdoor Precision Object Tracking for Rockfall Experiments
- PREM Intervals and Loop Tiling
- PREM Runtime Scheduling Policies
- PREM on PULP
- PULP-Shield for Autonomous UAV
- PULP Freertos with LLVM
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- PULP’s CLIC extensions for fast interrupt handling
- PVT Dynamic Adaptation in PULPv3
- Palm size chip NMR
- Passive Radar for UAV Detection using Machine Learning
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Peak-to-average power Reduction
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Phase-change memory devices for emerging computing paradigms
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of ITA (2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
- Positioning for the cellular Internet of Things
- Power Optimization in Multipliers
- Power Saver Mode for Cellular Internet of Things Receivers
- Practical Reconfigurable Intelligent Surfaces (RIS)
- Prasadar
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Precise Ultra-low-power Timer
- Predict eye movement through brain activity
- Predictable Execution on GPU Caches
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Probabilistic training algorithms for quantized neural networks
- Probing the limits of fake-quantised neural networks
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- Pulse Oximetry Fachpraktikum
- Putting Together What Fits Together - GrÆStl
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Quantum Transport Modeling of Interband Cascade Lasers (ICL)
- Quantum transport in 2D heterostructures
- RISC-V base ISA for ultra-low-area cores (2-3G)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- RVfplib
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Implementation of Quantum State Identification using an FPGA
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Real-Time Optical Flow Using Neural Networks
- Real-Time Pedestrian Detection For Privacy Enhancement
- Real-time Linux on RISC-V
- Real-time View Synthesis using Image Domain Warping
- Real-time eye movement analysis on a tablet computer
- Realtime Gaze Tracking on Siracusa
- Receiver design for the DigRF 4G high speed serial link
- Reconfigurability of SHA-3 candidates
- Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
- RedCap-5G for IOT application on prototype taped-out silicon
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Rethinking our Convolutional Network Accelerator Architecture
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Running Rust on PULP
- Runtime partitioning of L1 memory in Mempool (M)
- SCMI Support for Power Controller Subsystem
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- SSR combined with FREP in LLVM/Clang
- Satellite Internet of Things
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Scattering Networks for Scene Labeling
- Securing Block Ciphers against SCA and SIFA
- Self-Learning Drones based on Neural Networks
- Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
- Self Aware Epilepsy Monitoring
- Semi-Custom Digital VLSI for Processing-in-Memory
- Sensor Fusion for Rockfall Sensor Node
- Serverless Benchmarks on RISC-V (M)
