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Showing below up to 50 results in range #501 to #550.
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- On-Board Software for PULP on a Satellite
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- On-chip clock synthesizer design and porting
- On - Device Continual Learning for Seizure Detection on GAP9
- Online Learning of User Features (1S)
- OpenRISC SoC for Sensor Applications
- Open Power-On Chip Controller Study and Integration
- Optimal System Duty Cycling
- Optimal System Duty Cycling for a Mobile Health Platform
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Outdoor Precision Object Tracking for Rockfall Experiments
- PREM Intervals and Loop Tiling
- PREM Runtime Scheduling Policies
- PREM on PULP
- PULP-Shield for Autonomous UAV
- PULP Freertos with LLVM
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- PULP’s CLIC extensions for fast interrupt handling
- PVT Dynamic Adaptation in PULPv3
- Palm size chip NMR
- Passive Radar for UAV Detection using Machine Learning
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Peak-to-average power Reduction
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Phase-change memory devices for emerging computing paradigms
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of ITA (2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
- Positioning for the cellular Internet of Things
- Power Optimization in Multipliers
- Power Saver Mode for Cellular Internet of Things Receivers
- Practical Reconfigurable Intelligent Surfaces (RIS)
- Prasadar
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Precise Ultra-low-power Timer
- Predict eye movement through brain activity
- Predictable Execution on GPU Caches
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring