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4 KB (605 words) - 16:35, 20 February 2018
- ...hanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level d ...dictates battery size, the most critical factor in any volume-constrained system.4 KB (597 words) - 16:57, 12 July 2022
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0 bytes (0 words) - 14:44, 23 May 2018
- ..., non-invasive method to measure kidney performance via an external sensor system to avoid the use of urinary catheters for this subgroup of patients, thereb ...classification accuracy, and energy efficiency and to further optimize the system. The work includes the modeling and design of a suited impedance sensor, it6 KB (857 words) - 15:37, 10 November 2020
- ...roject focusses on the development of an unobtrusive multisensory embedded system to assist coaches to better quantify jumping trajectories of athletes. With ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.6 KB (820 words) - 12:13, 23 July 2023
- ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.6 KB (980 words) - 14:46, 2 June 2021
- #REDIRECT [[PULP in space - Fault Tolerant PULP System for Critical Space Applications]]88 bytes (13 words) - 13:10, 9 August 2019
- ...rphic intelligence using their processor to build a whole working embedded system. The student will deal with both hardware and software building a prototype * Motivation to build and test a real system5 KB (692 words) - 15:45, 10 November 2020
- ...ock diagram, which involves both the programming of a Low power FPGA and a System on Chip with ARM cortex-M4F and Bluetooth low energy 5.0. The project is qu * Motivation to build and test a real system4 KB (526 words) - 15:48, 10 November 2020
- <!-- Manycore System on FPGA --> At ETH, we are developing our own many-core system called MemPool [1]. It boasts 256 lightweight 32-bit Snitch cores developed8 KB (1,319 words) - 10:41, 6 July 2021
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- ...s is to have Halide programmed image processing kernels running on an HERO system implemented on an FPGA.5 KB (737 words) - 17:26, 2 November 2020
- <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> One of the most tedious and error-prone steps is assembling a peripheral system with the required and desired IO; this usually involves adapting existing p11 KB (1,675 words) - 15:40, 15 March 2021
- #REDIRECT [[Implementation of a Heterogeneous System for Image Processing on an FPGA (S)]]90 bytes (13 words) - 17:26, 2 November 2020
- ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.8 KB (1,196 words) - 10:41, 6 July 2021
- #REDIRECT [[Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)]]82 bytes (11 words) - 17:40, 2 November 2020
- ...ludes them from being used in a portable system. Furthermore, surveillance system typically do not come with any localized intelligence, so their recorded da In this project, a novel, distributed and energy-efficient surveillance system will be brought up and optimized by the student.3 KB (433 words) - 15:36, 4 August 2022
- <!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> ...unities are limited due to the necessity to retain major parts of the main system memory due to the use of static random access memory (SRAM) for code execut8 KB (1,127 words) - 19:54, 1 March 2023
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. The velocity of liquid flows (as for arteries and veins) can be measured b Preliminary results of custom syringe pump system:3 KB (363 words) - 17:18, 3 May 2024
- At ETH, we developed our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme ...d to integrate an FLL, a boot ROM, and a JTAG to access and initialize the system. While there are many IPs and know-how at IIS for that, this is also highly8 KB (1,239 words) - 12:36, 29 January 2024
- ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) --> ...ople.ee.ethz.ch/~janniss/projects/Maddness_system_integration.pdf Maddness System Intergration]6 KB (846 words) - 16:50, 3 November 2022
- <!-- AXI-based Network on Chip (NoC) system --> ...ould be to build a system with a mesh NoC and a couple of cores and do the system integration for a potential tapeout. For the verification, low-level softwa2 KB (252 words) - 14:43, 23 October 2023
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2 KB (250 words) - 09:31, 29 August 2023
- ...n technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of ...ane cores. Throughout this project, the feasibility and performance of the system shall be evaluated.2 KB (260 words) - 16:41, 15 November 2022
- ...Qubits will be read-out at the same time. For discrete Qubits, the readout system usually works at the sub-1 GHz frequency range. However, for a compact foot2 KB (372 words) - 10:32, 14 February 2023
- ...t needs to be accessed and monitored calls for a high-speed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]6 KB (720 words) - 16:27, 27 September 2023
- ...n a limited power budget require a novel approach across the entire stack, system-level design, and optimization. ...red offchip]] [[File:DistributedOnSensor.png|500px|thumb|right|Distributed System -> Only Region of Interest section of image is transferred offchip]]4 KB (577 words) - 18:28, 4 October 2023
- In this project, you will develop a smart agriculture system utilizing a sensor platform to optimize irrigation and pest control, aiming4 KB (534 words) - 17:09, 16 May 2024
- ...egrity. The end goal is to deploy these models into a real-time monitoring system capable of issuing alerts to maintenance teams, thus facilitating prompt an3 KB (465 words) - 11:47, 14 May 2024
- #REDIRECT [[Structural Health Monitoring (SHM) System (1-2S/M)]]64 bytes (9 words) - 11:47, 14 May 2024
- ...on of your project will be the development of a sophisticated notification system designed to automatically alert both local authorities and the public about * '''Automated Warning System:''' Develop a notification system that automatically alerts local authorities and the public of potential dan4 KB (531 words) - 17:09, 16 May 2024
Page text matches
- ...tion of the FPUs and therefore reduce the overall power consumption of the system. Sharing FPUs allows to employ several different units, which can be either ...nd is a promising approach to further improve the energy efficiency of the system. One way to approximate FP-operations is to use Newton's method to compute3 KB (377 words) - 10:58, 21 February 2018
- ...egory:Qcrypt|QCRYPT]] was the development of the 100 Gbit/s link encryptor system with a variety of optical interfaces on the plain-text side and a 100 Gbit ...main focus lay on the development of a second version of the PCB for this system. The layer stackup was modified to enhance the high-frequency quality of th2 KB (359 words) - 20:06, 17 February 2015
- ''2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)'', Santa Cruz, California, USA, 7-10 Oct 20123 KB (392 words) - 12:25, 26 March 2015
- ...erent mobile platforms, most productions are captured with one acquisition system at fixed parameters. Examples for content adaption algorithms are content-a ...ons and VLSI Implementations", ''VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, volume 418 of IFIP Advances in Information and Communicatio4 KB (520 words) - 16:04, 13 May 2015
- ...IC/FPGA system which implements the first three steps of this process. Our system is able to extract SKB features from one 720p video stream in real time (303 KB (487 words) - 15:57, 13 May 2015
- ...ing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparen1 KB (193 words) - 15:39, 3 March 2020
- ...the image is being acquired and forward this information to a larger host system for further processing. ...algorithm steps directly ion hardware and interface with the host computer system.3 KB (357 words) - 18:53, 6 December 2014
- ...bits. Such data converters are intended to be embedded in a mostly digital system, and this legitimates the adoption of ultra-scaled CMOS technologies from w2 KB (277 words) - 17:28, 29 January 2014
- Although the wireless and battery-powered nature of this system reduces the impact of mains interference, its amplitude might nonetheless b ...ed by an off-the-shelf mobile phone battery which is sufficient to run the system for several hours - the battery life-time is mainly limited by the Bluetoot2 KB (280 words) - 10:54, 10 March 2015
- his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular894 bytes (115 words) - 17:17, 30 November 2021
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (597 words) - 12:56, 4 December 2021
- ...upper layers of the OsmocomBB GSM protocol stack. The functionality of the system is verified with a testbed comprising a base station and a receiver board w3 KB (360 words) - 14:14, 27 May 2015
- ...ssor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Sign3 KB (397 words) - 14:12, 27 May 2015
- ...ons such as those in the time-duplexing high speed packet access (TD-HSPA) system.2 KB (266 words) - 10:43, 9 February 2015
- ...terms of parallelism, performances and robustness. One has to revisit the system design in terms of usage of hardware accelerators, heterogeneous or homogen4 KB (568 words) - 12:48, 9 February 2015
- ...communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates.]] ...Q operation that is critical for the average throughput performance of the system.2 KB (343 words) - 13:56, 9 February 2015
- ...channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations.]] ...ion-specific cost functions) substantially increases the robustness of the system to unreliable memory operation, compared to the data representations most c3 KB (352 words) - 13:56, 9 February 2015
- ...t role in this type of devices and in general in battery-operated embedded system. : Interest in Computer Architectures at system level2 KB (342 words) - 16:46, 11 February 2015
- ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.3 KB (487 words) - 12:02, 27 January 2016
- ...a low power radio wake up receiver can reduce the power consumption of the system while still keeping its response time low. Another role of the wake-up radi ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe4 KB (613 words) - 19:54, 9 February 2015
- ...ices while still keeping its wake up time low. Another role of the wake-up system is that based on "intelligence" to select a specific device which has to be ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe3 KB (515 words) - 19:55, 9 February 2015
- [[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]] ...rrently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiv3 KB (373 words) - 11:51, 19 August 2017
- ...o experienced students) comprises the implementation of such a measurement system. Possible approaches include a cross-correlating spectrum analyzer or the u2 KB (251 words) - 20:06, 17 February 2015
- ...uld be to evaluate and integrate this camera into a working scene labeling system [[http://dl.acm.org/citation.cfm?id=2744788 paper]] and would be very diver * create a system from the individual parts (build a case/box mounting the cameras, dev board6 KB (941 words) - 11:29, 5 February 2016
- ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence5 KB (784 words) - 14:50, 30 November 2016
- [[Category:Biomedical System on Chips]]2 KB (278 words) - 16:57, 12 July 2022
- [[Category:System Design]]2 KB (348 words) - 20:01, 26 September 2017
- * Designing the system architecture * Defining the circuit using hardware description languages (HDL) such as (System Verilog or VHDL) for [[:Category:Digital|digital projects]], and schematic1 KB (165 words) - 19:52, 10 February 2015
- * Understand the different available peripherals on your system board * Run your system on the development board and collect the results.1,020 bytes (132 words) - 19:50, 10 February 2015
- ...will be able to control the accelerator from the command line of the Linux system. :[3] [http://www.arm.com/products/system-ip/amba/amba-open-specifications.php ARM AMBA Specification]2 KB (236 words) - 09:46, 12 October 2017
- [[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]] * [http://asic.ethz.ch/2020/Thestral.html Thestral] Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed t10 KB (1,563 words) - 10:09, 19 August 2022
- [[Category:System Design]]3 KB (449 words) - 12:12, 4 November 2019
- ...r OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can co : For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the4 KB (667 words) - 15:23, 23 December 2016
- In recent years reseach works shows that thermal evolution of a multicore system can be effectively modelled with linear state-space representation enabling ...will then be part of a larger system and be part of the thermal management system. In this project the goal is to implement a novel MPC algorithm in hardware3 KB (456 words) - 08:35, 20 January 2021
- ..., R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/02 KB (350 words) - 17:56, 14 April 2016
- ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ...f wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmis3 KB (369 words) - 18:11, 1 March 2023
- ...method by implementing our system.. Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe : Interest in Computer Architectures at system level3 KB (378 words) - 19:56, 9 February 2015
- Reliability (R(t)) is the probability that a given system does not fail before time t. It is becoming a major concern in modern multi ...bile]] [[Category:Temperature]] [[Category:Dynamic Management]] [[Category:System Design]]4 KB (573 words) - 17:24, 9 February 2015
- ...s an heterogeneous thermal profile which is highly dependent on the actual system usage. As a matter of fact today and future mobile devices are thermally li ...thermal model can be directly identified from the target device by mean of system identification and self-calibrating routines.3 KB (452 words) - 11:03, 10 February 2015
- [[Category:System Design]]3 KB (408 words) - 13:17, 5 February 2016
- ...stem was proposed alongside the release-8 of the Long Term Evolution (LTE) system for the fourth generation (4G) of mobile communication. While the air inter ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf1 KB (159 words) - 11:16, 23 September 2016
- [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo3 KB (384 words) - 16:41, 17 July 2016
- ...E transceiver [2] will be used. You will start with your design by doing a system analysis on the required building blocks (Synchronization, FFT, Symbol dete [[Category:System Design]]3 KB (335 words) - 14:20, 4 November 2019
- : Matlab, C++, VHDL or System Verilog2 KB (351 words) - 13:09, 2 November 2015
- : Matlab, C++, VHDL or System Verilog2 KB (328 words) - 12:38, 1 June 2017
- ...er, a careful design of each regulator is extremely important. A PCB-based system, containing of-the-shelf converter chips where available, and discrete-comp [[Category:System Design]]3 KB (438 words) - 18:06, 3 February 2015
- ...be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, and reduce the total energy consumption.3 KB (431 words) - 18:04, 28 January 2017
- [[Category:System Design]]4 KB (589 words) - 10:14, 3 August 2018
- : Interest in Computer Architectures at system level : Wearable system I (prof. Troester lectures)2 KB (319 words) - 16:24, 30 October 2020
- [[File:mvSystem.jpg|thumb|600px|a) Multiview system in action and b) closeup of the hardware prototype.]] Ideally, a 3D display system should not require the users to3 KB (509 words) - 09:09, 23 October 2015
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]7 KB (816 words) - 11:57, 8 May 2024
- ...event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). It plays a crucial role in enabling agile design space exp * Experience with System Verilog is recommended but not strictly necessary4 KB (520 words) - 15:15, 4 December 2023
- ...k, Nitin Mangalvedhe, Amitava Ghosh, and Benny Vejlgaard. Narrowband LTE-M system for M2M communication. 2014.4 KB (561 words) - 10:43, 6 November 2017
- is indispensable. Ideally, System-on-a-Chip (SoC) or System-in-a-Package (SiP) modems such as [1] are7 KB (1,105 words) - 20:02, 26 September 2017
- [[Category:Digital]] [[Category:System Design]]5 KB (707 words) - 11:22, 5 February 2016
- [[Category:System Design]]1 KB (169 words) - 16:42, 9 December 2015
- ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.5 KB (716 words) - 13:43, 29 November 2019
- ...e piezoelectric elements in the transducer head are connected to a backend system over a large cable containing hundreds of small coaxial cables. This is sho In order to do so, the entire analog frontend of the ultrasound system needs to be integrated into the transducer head and a digital link needs to3 KB (378 words) - 11:52, 10 January 2017
- ...tation of an entire scene labeling network. In order to keep the developed system flexible in terms of the convolutional neural network that is applied as we ...rt software blocks to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.8 KB (1,197 words) - 18:18, 29 August 2016
- [[Category:System Design]]3 KB (420 words) - 11:22, 14 April 2016
- ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e This system design project requires work to be done at several layers of abstraction. M4 KB (585 words) - 17:57, 7 November 2017
- ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e : VHDL/System Verilog, C4 KB (554 words) - 17:57, 7 November 2017
- ...ment of novel zero-power sensors that act as a trigger for the rest of the system when an important event is detected and consume zero-power between two dete ...classification accuracy and energy efficiency and to further optimize the system.6 KB (774 words) - 08:36, 23 November 2022
- [[Category:System Design]] [[Category:System Design]]4 KB (471 words) - 11:13, 3 May 2018
- ...we have implemented and fabricated an 8-channel biosignal acquisition SoC (System-on-Chip) [http://asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including ana2 KB (353 words) - 08:35, 20 January 2021
- [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Luk [[Category:Digital]] [[Category:System Design]]4 KB (563 words) - 11:29, 5 February 2016
- ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level3 KB (448 words) - 11:59, 28 July 2015
- : Interest in Computer Architectures at system level ...arning would be beneficial (i.e. semester project or exam done in Wearable system I prof. Troester)3 KB (380 words) - 11:59, 28 July 2015
- [[Category:System Design]]4 KB (507 words) - 12:11, 16 February 2016
- ...otal power spent for event detection, we propose an alternative, two-stage system architecture consisting of: 1. "wake-up sensing" (WUS) circuit, and 2. main [[Category:System Design]]7 KB (895 words) - 17:02, 28 July 2017
- ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]8 KB (1,176 words) - 16:26, 30 October 2020
- ...by canceling self-induced motion blur. The VOR is driven by the vestibular system and induces short-latency eye movements in the opposite direction to the he2 KB (376 words) - 14:43, 29 July 2015
- ...l-diversity streams have been introduced with the Evolved EDGE 2G cellular system [1], the recent EC-GSM-IoT standard achieves up to 20 dB coverage extension3 KB (418 words) - 10:39, 6 November 2017
- ...ration of the communication portion of the node is indispensable. Ideally, System-on-a-Chip (SoC) modems are used.2 KB (299 words) - 17:58, 14 April 2016
- [[Category:System Design]]3 KB (390 words) - 11:59, 20 June 2016
- [[Category:System Design]]4 KB (593 words) - 14:57, 30 November 2016
- ...lly, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the corresponding software inter : Matlab, C++, VHDL or System Verilog4 KB (542 words) - 12:39, 1 June 2017
- ...stablished method to save power in circuit parts currently not in use in a system on chip (SoC). In contrast to clock gating, where the clock signal is disab2 KB (364 words) - 09:34, 25 July 2017
- Memories are central building blocks of any processing system, in fact most of the performance of a modern processor is determined by its5 KB (769 words) - 15:54, 23 May 2018
- [[Category:System Design]]2 KB (340 words) - 11:55, 21 August 2018
- [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results3 KB (397 words) - 18:17, 29 August 2016
- <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Mas2 KB (285 words) - 18:16, 29 August 2016
- [1] 3GPP. Cellular System Support for Ultra Low Complexity and Low Throughput Internet of Things. htt4 KB (582 words) - 20:00, 26 September 2017
- [[File:iPMU.png|600px|thumb|right|iPMU within a Generalized System]] ...ilable energy for the system and learn the energy consumption of different system tasks. Moreover, the iPMU should profile the available power input from the2 KB (292 words) - 11:40, 2 June 2021
- ...such as battery or supercapacitor for future use. A correctly dimensioned system will guarantee the node’s operation during periods of energy unavailabili3 KB (366 words) - 18:04, 28 January 2017
- ...rs. In our lab, we have developed a energy management unit, which allows a system designer to provide energy guarantees solely from volatile energy harvestin [[Category:System Design]]3 KB (413 words) - 15:21, 28 January 2016
- [[Category:Software]] [[Category:System]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2016]] * Interest in computer vision and system engineering5 KB (747 words) - 18:04, 29 August 2016
- [[Category:System Design]]3 KB (426 words) - 11:41, 21 July 2017
- : VHDL/System Verilog knowledge3 KB (377 words) - 10:25, 5 November 2019
- ...ultra low power consumption are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is : VHDL/System Verilog knowledge3 KB (384 words) - 17:24, 21 August 2019
- ...wn approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel [[Category:System Design]]3 KB (450 words) - 11:43, 13 November 2018
- ...w evaluation platform based on the Juno ARM Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F : VHDL/System Verilog, C5 KB (711 words) - 10:27, 5 November 2019
- [[Category:System Design]]3 KB (402 words) - 15:31, 13 April 2016
- [[Category:System Design]]3 KB (418 words) - 14:01, 13 November 2020
- Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power c *Control system DMA to save/restore L1 data memory2 KB (236 words) - 08:35, 20 January 2021
- ...o maintain as much as possible the general purpouse phylosofy of the whole system.2 KB (237 words) - 10:27, 5 November 2019
- [[Category:System Design]]4 KB (555 words) - 16:36, 23 May 2018
- ...tion of the FPUs and therefore reduce the overall power consumption of the system. We have already designed a FPU unit with support for FP-additions, FP-subt ...dware efficient architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.2 KB (346 words) - 10:26, 5 November 2019
- : Knowledge of a hardware design language such as (System)Verilog or VHDL. [[Category:System Design]]4 KB (522 words) - 13:38, 10 November 2020
- [[Category:System Design]]3 KB (403 words) - 20:45, 9 August 2016