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• Creating a HDMI Video Interface for PULP
  ...ns. Unfortunately at the moment we are lacking any serious user-interfaces and we are constantly falling back to a standard UART (serial) interface. Your task would consist of interfacing such a transmitter and supplying it with data from an on-chip (or external) frame-buffer. At first
  4 KB (603 words) - 09:37, 10 July 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...partment of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real world, then this is your chance ...The Xilinx AC701 Development Board in combination with a recently designed and build interface board (see picture) will be used for the project. The work
  4 KB (460 words) - 21:42, 30 January 2018
• Aliasing-Free Wavetable Music Synthesizer
  ...esizers, such as the Waldorf Quantum, the UDO SUPER 6, the ASM hydrasynth, and the Nord Wave 2 (just to name a few). While most of these synthesizers rely ...while offering great flexibility. In the second step, a VLSI architecture and ASIC will be designed. The goal is to include easy reconfigurability of the
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  ...of "operators," which describe how various (typically 4-to-8) oscillators and envelope generators interact with each other. This project will develop the ...d, the student(s) will implement the architecture in a modern CMOS process and send the modular FM synthesis ASIC to fabrication.
  5 KB (549 words) - 12:35, 28 November 2022
• Hyperdimensional Computing
  ...arallel operations and is extremely robust against most failure mechanisms and noise. ...ng a prime candidate for utilization in application domains such as: brain-computer interfaces, biosignal processing (e.g., EEG/ECoG/EMG), robotics, voice/vide
  10 KB (1,341 words) - 10:46, 25 April 2018
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...uperconducting circuits by the implementation of optimal linear processing and thresholding of measured signals, followed by signal histogram generation a ...nal processing results. The interface between the FPGA and ADC board, DDR3 and PC is already implemented.
  5 KB (599 words) - 09:03, 21 December 2017
• Extend the RI5CY core with priviledge extensions
  ...rs that implements the RISC-V ISA. It has been designed for small embedded system platforms mostly used in IoT devices. Its ISA implements RISC-V's RV32IMFC Recently RI5CY as well as the PULP platforms have been chosen and/or evaluated by big companies like Google, IBM, micron, NXP, Dolphin Integr
  4 KB (661 words) - 08:38, 20 January 2021
• Wearables for Sports and Life Enhancement
  Wearables for Sports and Life Enhancement [[Category:Computer Architecture]]
  3 KB (381 words) - 14:17, 28 January 2023
• Physics is looking for PULP
  ...prove the quality of results, accelerate the rate at which data is sampled and allow new physical phenomena to be observed. ...planned to make this infrastructure openly available for other educational and research institutions.
  4 KB (497 words) - 16:50, 21 June 2018
• Analog Compute-in-Memory Accelerator Interface and Integration
  ...n-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm. ...nt state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].
  3 KB (352 words) - 18:02, 16 December 2022
• Elliptic Curve Accelerator for zkSNARKs
  ...he correctness of the transaction: the input and output values add to zero and the sender actually owns the coins that he spends. ZCash would enable a dis ...wever: creating a zkSNARK requires a lot of computational power and energy and software implementations take 10s of seconds on a current processors. A lot
  5 KB (614 words) - 15:02, 4 March 2019
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  ...tories of athletes. Within the short duration of a ski-jump (< 10 seconds) and exposed to the conditions of nature (snow, wind, temperature) athletes must ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.
  6 KB (820 words) - 12:13, 23 July 2023
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  ...models the behavior of these networks. Individual network blocks are built and cascaded as single blackbox models using Python [https://scikit-rf.org/ sci ...system can be adapted in operation for a wide variety of transducer types and setups.
  5 KB (644 words) - 18:18, 21 July 2023
• NAND Flash Open Research Platform
  ...hat allows to directly interface to NAND flash ICs to study their behavior and argue about their security. ...rd able to interface with raw NAND flash chips. In particular, read, write and re-program them directly. This project would involve designing a PCB daught
  4 KB (551 words) - 11:06, 11 July 2019
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  ...d DHBTs, including their cut-off frequencies, breakdown voltages, vertical and lateral scalabilities, etc. ...Leveraging this simulation scheme, various DHBT systems could be simulated and potential design ameliorations could be proposed.
  4 KB (517 words) - 17:09, 16 September 2021
• NVDLA meets PULP
  [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] ...on, competitor, accelerator, or encompassing framework to the PULP project and the accelerators/processors we have developed.
  6 KB (799 words) - 13:42, 10 November 2020
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  ...security and multimedia entertaining as well as biomedical devices as ECG and EEG wearable devices for health care applications are just few of these exa ...until it finally arrives to the server in the cloud which will process it and possibly give feedbacks to the users or to the microcontroller for closed-l
  7 KB (1,030 words) - 19:05, 29 January 2021
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  ...high level semantically rich information out of raw data is deep learning, and in particular deep convolutional neural networks (CNNs). The task of infere ...design a PULP-based entire computation cluster around a set of deep, fast and low-power deep learning engines.
  7 KB (961 words) - 21:21, 29 January 2019
• Timing Channel Mitigations for RISC-V Cores
  ...hniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. ...act''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '
  6 KB (915 words) - 18:16, 20 May 2020
• Developing a small portable neutron detector for detecting smuggled nuclear material
  ...preferably has an appropriate user interface, battery power for mobility, and data-logging/communication with a central location for analysis of data fro * Familiarization with the physics and current signal processing setup of the detector prototype
  5 KB (623 words) - 10:32, 5 November 2019

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