Category:Semester Thesis
From iis-projects
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Semester thesis at the IIS is for 1-3 students for a duration of 14 weeks and should take 50% of the time of the students. The available projects in this category are meant primarily for a semester thesis. However if you are interested in the topic, you can discuss with the supervisor, in most cases the content of the project can be expanded to fit a master thesis as well.
Pages in category "Semester Thesis"
The following 53 pages are in this category, out of 524 total.
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- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A Recurrent Neural Network Speech Recognition Chip
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A Wireless Sensor Network for HPC monitoring
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accelerators for object detection and tracking
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Advanced Data Movers for Modern Neural Networks
- Advanced EEG glasses
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Air Quality Prediction in Office Rooms (1-2S/M)
- All the flavours of FFT on MemPool (1-2S/B)
- Ambient RF Energy harvesting for Wireless Sensor Network
- AMZ Driverless Competition Embedded Systems Projects
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- An Efficient Compiler Backend for Snitch (1S/B)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Evaluation Platform for Mobile Communications
- An Industrial-grade Bluetooth LE Mesh Network Solution
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Analog building blocks for mmWave manipulation
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analog Layout Engine
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders