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Create the page "FPGA & Digital ASIC Design" on this wiki! See also the search results found.
- have to rely on low-resolution analog-to-digital converters (ADCs). However, the use of such low-resolution ADCs creates new ...G. Durisi, T. Goldstein, and C. Studer, "Hybrid Jammer Mitigation for All-Digital mmWave Massive MU-MIMO", 2021 Asilomar Conference on Signals, Systems, and5 KB (662 words) - 13:33, 10 May 2023
- * '''[[Design Review]]''' [[Category:Digital]]5 KB (586 words) - 15:34, 11 July 2022
- [[Category:Digital]] [[Category:ASIC]]8 KB (1,304 words) - 14:44, 23 October 2023
- [[Category:Digital]] [[Category:FPGA]]3 KB (416 words) - 10:49, 25 January 2024
- Digital sound synthesis is widely used in modern music production, with many popula The goals of this project are to design, optimize, and implement aliasing-free oscillator synchronization of arbitr5 KB (577 words) - 09:48, 5 October 2022
- [[Category:Digital]] ...-physical address translation. As it seems, it’s a very complex block to design and handle.5 KB (769 words) - 11:38, 3 November 2023
- [[Category:Digital]] ...itly defined in software, for which several DMA engines are provided. This design decision improves overall energy efficiency.7 KB (944 words) - 10:47, 25 January 2024
- <!-- Radiation Testing of a PULP ASIC (1S) --> [[Category:Digital]]3 KB (454 words) - 14:59, 25 October 2023
- ...ls, small rooms, caves, etc.) or improving realism. However, most existing digital signal processing (DSP)-based reverberation techniques require large amount The goal of this project is to design and implement a novel artificial reverberation algorithm that requires a mi5 KB (578 words) - 12:39, 14 June 2023
- <!-- FPGA mapping of RPC DRAM (1-2S/B) --> [[Category:Digital]]3 KB (484 words) - 20:29, 21 February 2024
- ...ed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]6 KB (720 words) - 16:27, 27 September 2023
- : Embedded systems and PCB design * '''[[Design Review]]'''6 KB (688 words) - 12:15, 23 July 2023
- ...g the speed and design effort bottlenecks of cycle-accurate simulators and FPGA prototypes, respectively, while preserving functional and timing accuracy. ...show that GVSoC enables practical functional and performance analysis and design exploration at the full-platform level (processors, memory, peripherals and14 KB (2,018 words) - 22:54, 23 November 2023
- : Embedded systems and PCB design : 40% Hardware and PCB Design6 KB (735 words) - 12:15, 23 July 2023
- : 30% Mechanical Design ...of coupling media in terms of: acoustic properties (e.g., attenuation), 3d design and integration, farbication complexity, cost.5 KB (631 words) - 12:43, 23 July 2023
- * Showing participation in non-curricular analog/digital projects is a plus. * Circuit design tools (e.g., Altium Designer).7 KB (903 words) - 10:04, 24 July 2023
- : 30% Mechanical Design ...of coupling media in terms of: acoustic properties (e.g., attenuation), 3d design and integration, farbication complexity, cost.5 KB (631 words) - 10:07, 24 July 2023
- ...hoice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed. ...or-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at signific3 KB (356 words) - 14:53, 11 October 2023
- [[Category:Digital]] [[Category:ASIC]]2 KB (314 words) - 18:47, 24 November 2023