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Showing below up to 50 results in range #41 to #90.
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- Design and Implementation of ultra low power vision system (16:46, 11 February 2015)
- Audio (17:28, 11 February 2015)
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces (20:06, 17 February 2015)
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator (20:06, 17 February 2015)
- Audio DAC Conversion Jitter Measurement System (20:06, 17 February 2015)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems (20:10, 17 February 2015)
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC (10:04, 18 February 2015)
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC (10:06, 18 February 2015)
- Norbert Felber (13:56, 18 February 2015)
- Philipp Schönle (10:52, 10 March 2015)
- Flexible Front-End Circuit for Biomedical Data Acquisition (10:53, 10 March 2015)
- Wireless Biomedical Signal Acquisition Device (10:54, 10 March 2015)
- Benjamin Sporrer (13:01, 10 March 2015)
- High Performance Cellular Receivers in Very Advanced CMOS (13:02, 10 March 2015)
- Telecommunications (17:42, 24 March 2015)
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC (19:45, 24 March 2015)
- Putting Together What Fits Together - GrÆStl (12:01, 26 March 2015)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (12:09, 26 March 2015)
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers (12:25, 26 March 2015)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (12:26, 26 March 2015)
- A Trustworthy Three-Factor Authentication System (14:01, 26 March 2015)
- A Multiview Synthesis Core in 65 nm CMOS (15:49, 13 May 2015)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment (15:57, 13 May 2015)
- Real-time View Synthesis using Image Domain Warping (16:04, 13 May 2015)
- Evolved EDGE Physical Layer Incremental Redundancy Architecture (14:12, 27 May 2015)
- MatPHY: An Open-Source Physical Layer Development Framework (14:14, 27 May 2015)
- Autonomous Smart Watches: Hardware and Software Desing (11:59, 28 July 2015)
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors (11:59, 28 July 2015)
- Eye movements (14:43, 29 July 2015)
- RazorEDGE: An Evolved EDGE DBB ASIC (17:15, 1 September 2015)
- Hardware/software co-programming on the Parallella platform (14:26, 2 September 2015)
- Real-Time Stereo to Multiview Conversion (09:09, 23 October 2015)
- Active-Set QP Solver on FPGA (13:09, 2 November 2015)
- Vector Processor for In-Memory Computing (13:10, 2 November 2015)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (16:42, 9 December 2015)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC (17:07, 17 December 2015)
- EvalEDGE: A 2G Cellular Transceiver FMC (17:10, 17 December 2015)
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications (18:15, 17 December 2015)
- A Wireless Sensor Network for a Smart LED Lighting control (12:02, 27 January 2016)
- Bateryless Heart Rate Monitoring (15:21, 28 January 2016)
- Real-Time Optical Flow Using Neural Networks (11:22, 5 February 2016)
- Scattering Networks for Scene Labeling (11:29, 5 February 2016)
- Improving Scene Labeling with Hyperspectral Data (11:29, 5 February 2016)
- FFT-based Convolutional Network Accelerator (11:30, 5 February 2016)
- Real-Time Pedestrian Detection For Privacy Enhancement (13:17, 5 February 2016)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (12:11, 16 February 2016)
- Low-power Clock Generation Solutions for 65nm Technology (19:37, 3 March 2016)
- Final Report (10:22, 10 March 2016)
- NextGenChannelDec (15:31, 13 April 2016)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (11:12, 14 April 2016)
