Short pages

Showing below up to 50 results in range #451 to #500.

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451. (hist) ‎Digital Beamforming for Ultrasound Imaging ‎[3,167 bytes]
452. (hist) ‎Shared Correlation Accelerator for an RF SoC ‎[3,167 bytes]
453. (hist) ‎Efficient TNN compression ‎[3,170 bytes]
454. (hist) ‎Implementation of a 2-D model for Li-ion batteries ‎[3,173 bytes]
455. (hist) ‎Satellite Internet of Things ‎[3,173 bytes]
456. (hist) ‎LightProbe - Frontend Firmware and Control Side Channel ‎[3,177 bytes]
457. (hist) ‎Engineering For Kids ‎[3,177 bytes]
458. (hist) ‎Deep Learning for Brain-Computer Interface ‎[3,180 bytes]
459. (hist) ‎Bateryless Heart Rate Monitoring ‎[3,181 bytes]
460. (hist) ‎PULP Freertos with LLVM ‎[3,185 bytes]
461. (hist) ‎Thermal Control of Mobile Devices ‎[3,195 bytes]
462. (hist) ‎NextGenChannelDec ‎[3,196 bytes]
463. (hist) ‎Low-Power Environmental Sensing ‎[3,205 bytes]
464. (hist) ‎Advanced EEG glasses ‎[3,216 bytes]
465. (hist) ‎FPGA Testbed Implementation for Bluetooth Indoor Positioning ‎[3,221 bytes]
466. (hist) ‎IoT Turbo Decoder ‎[3,235 bytes]
467. (hist) ‎Augmenting Our IPs with AXI Stream Extensions (M/1-2S) ‎[3,235 bytes]
468. (hist) ‎Using Motion Sensors to Support Indoor Localization ‎[3,236 bytes]
469. (hist) ‎NORX - an AEAD algorithm for the CAESAR competition ‎[3,243 bytes]
470. (hist) ‎Ultrasound-EMG combined hand gesture recognition ‎[3,244 bytes]
471. (hist) ‎High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT ‎[3,248 bytes]
472. (hist) ‎Design of combined Ultrasound and Electromyography systems ‎[3,250 bytes]
473. (hist) ‎Gomeza old project1 ‎[3,251 bytes]
474. (hist) ‎FPGA Optimizations of Dense Binary Hyperdimensional Computing ‎[3,251 bytes]
475. (hist) ‎Heterogeneous SoCs ‎[3,257 bytes]
476. (hist) ‎Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) ‎[3,265 bytes]
477. (hist) ‎CLIC for the CVA6 ‎[3,299 bytes]
478. (hist) ‎Neural Recording Interface and Signal Processing ‎[3,302 bytes]
479. (hist) ‎VLSI Implementation of a 5G Ciphering Accelerator ‎[3,312 bytes]
480. (hist) ‎Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip ‎[3,329 bytes]
481. (hist) ‎Simulation of Negative Capacitance Ferroelectric Transistor ‎[3,335 bytes]
482. (hist) ‎Linux Driver for fine-grain and low overhead access to on-chip performance counters ‎[3,337 bytes]
483. (hist) ‎LTE IoT Network Synchronization ‎[3,346 bytes]
484. (hist) ‎Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) ‎[3,351 bytes]
485. (hist) ‎Next Generation Channel Decoder ‎[3,360 bytes]
486. (hist) ‎A Wireless Sensor Network for a Smart LED Lighting control ‎[3,364 bytes]
487. (hist) ‎Multi issue OoO Ariane Backend (M) ‎[3,365 bytes]
488. (hist) ‎Low-power chip-to-chip communication network ‎[3,375 bytes]
489. (hist) ‎Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) ‎[3,375 bytes]
490. (hist) ‎Ab-initio Simulation of Strained Thermoelectric Materials ‎[3,382 bytes]
491. (hist) ‎Low-power Clock Generation Solutions for 65nm Technology ‎[3,387 bytes]
492. (hist) ‎Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device ‎[3,394 bytes]
493. (hist) ‎FPGA mapping of RPC DRAM ‎[3,396 bytes]
494. (hist) ‎Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) ‎[3,396 bytes]
495. (hist) ‎Real-time Linux on RISC-V ‎[3,402 bytes]
496. (hist) ‎Charge and heat transport through graphene nanoribbon based devices ‎[3,419 bytes]
497. (hist) ‎Compiler Profiling and Optimizing ‎[3,423 bytes]
498. (hist) ‎Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment ‎[3,425 bytes]
499. (hist) ‎Hardware Accelerator for Model Predictive Controller ‎[3,433 bytes]
500. (hist) ‎Cell Measurements for the 5G Internet of Things ‎[3,433 bytes]

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