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From iis-projects
Showing below up to 50 results in range #481 to #530.
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- (hist) Simulation of Negative Capacitance Ferroelectric Transistor [3,335 bytes]
- (hist) Linux Driver for fine-grain and low overhead access to on-chip performance counters [3,337 bytes]
- (hist) LTE IoT Network Synchronization [3,346 bytes]
- (hist) Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) [3,351 bytes]
- (hist) Next Generation Channel Decoder [3,360 bytes]
- (hist) A Wireless Sensor Network for a Smart LED Lighting control [3,364 bytes]
- (hist) Multi issue OoO Ariane Backend (M) [3,365 bytes]
- (hist) Low-power chip-to-chip communication network [3,375 bytes]
- (hist) Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) [3,375 bytes]
- (hist) Ab-initio Simulation of Strained Thermoelectric Materials [3,382 bytes]
- (hist) Low-power Clock Generation Solutions for 65nm Technology [3,387 bytes]
- (hist) Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device [3,394 bytes]
- (hist) FPGA mapping of RPC DRAM [3,396 bytes]
- (hist) Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) [3,396 bytes]
- (hist) Real-time Linux on RISC-V [3,402 bytes]
- (hist) Charge and heat transport through graphene nanoribbon based devices [3,419 bytes]
- (hist) Compiler Profiling and Optimizing [3,423 bytes]
- (hist) Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment [3,425 bytes]
- (hist) Hardware Accelerator for Model Predictive Controller [3,433 bytes]
- (hist) Cell Measurements for the 5G Internet of Things [3,433 bytes]
- (hist) Hyper Meccano: Acceleration of Hyperdimensional Computing [3,434 bytes]
- (hist) Processing of 3D Micro-tomography data for Lithium Ion Batteries [3,438 bytes]
- (hist) Infrared Wake Up Radio [3,454 bytes]
- (hist) Routing 1000s of wires in Network-on-Chips (1-2S/M) [3,457 bytes]
- (hist) Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs [3,470 bytes]
- (hist) Zephyr RTOS on PULP [3,478 bytes]
- (hist) Structural Health Monitoring (SHM) System (1-2S/M) [3,478 bytes]
- (hist) Resilient Brain-Inspired Hyperdimensional Computing Architectures [3,480 bytes]
- (hist) Wearables in Fashion [3,486 bytes]
- (hist) Open Power-On Chip Controller Study and Integration [3,490 bytes]
- (hist) FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things [3,491 bytes]
- (hist) SCMI Support for Power Controller Subsystem [3,507 bytes]
- (hist) Real-Time Stereo to Multiview Conversion [3,509 bytes]
- (hist) Neural Recording Interface and Spike Sorting Algorithm [3,516 bytes]
- (hist) Runtime partitioning of L1 memory in Mempool (M) [3,522 bytes]
- (hist) Gomeza old project4 [3,523 bytes]
- (hist) Indoor Positioning with Bluetooth [3,531 bytes]
- (hist) Turbo Equalization for Cellular IoT [3,536 bytes]
- (hist) All the flavours of FFT on MemPool (1-2S/B) [3,536 bytes]
- (hist) Ultra Low Power Conversion Circuit For Batteryless Applications [3,549 bytes]
- (hist) FFT HDL Code Generator for Multi-Antenna mmWave Communication [3,553 bytes]
- (hist) Big Data Analytics Benchmarks for Ara [3,556 bytes]
- (hist) Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors [3,559 bytes]
- (hist) ASIC Implementation of High-Throughput Next Generation Turbo Decoders [3,562 bytes]
- (hist) Wearables for Sports and Life Enhancement [3,562 bytes]
- (hist) Hardware/software co-programming on the Parallella platform [3,565 bytes]
- (hist) NeuroSoC RISC-V Component (M/1-2S) [3,567 bytes]
- (hist) Efficient Banded Matrix Multiplication for Quantum Transport Simulations [3,572 bytes]
- (hist) 3D Matrix Multiplication Unit for ITA (1S) [3,582 bytes]
- (hist) Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy [3,597 bytes]
