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• EECIS
  category = In progress category = In progress
  740 bytes (70 words) - 15:18, 25 September 2019
• User:Paulin
  ...ing of 2019. Inbetween my Bachelor and Master degree I worked for 6 months in the Digital Design team at U-Blox as an Intern. My main interests lay in reduced precision deep learning from the algorithmic and hardware accelerat
  2 KB (193 words) - 16:00, 16 November 2020
• User:Prasadar
  ...ETHZ), Switzerland in March 2021. After that, I started as a Ph.D. Student in the Digital Circuits and Systems Group of Prof. Dr. L. Benini. ...rchitecture exploration using system simulation. To summarize my interests in a few keywords
  1 KB (194 words) - 16:59, 12 December 2023
• User:Yiczhang
  ...ived my M.Sc. in electronics at Nanyang Technological University Singapore in 2017. I have worked at MediaTek Inc. and Cadence Design System focusing on Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini
  1 KB (211 words) - 15:20, 31 October 2023
• User:Fischeti
  ...d my Master's degree in April 2020. After that, I started as a PhD Student in the digital circuits and systems group of Prof. Dr. L. Benini My research focuses on interconnects for on-chip and off-chip communication in HPC Systems. Specifically, I am currently working on Network-on-Chips (NoCs
  2 KB (211 words) - 17:00, 3 November 2023
• Hardware Support for IDE in Multicore Environment
  [[File:Hardware support for IDE in multicore.jpg|thumb]] ===Status: In Progress ===
  2 KB (188 words) - 10:58, 27 March 2014
• Fault Tolerance
  ...ors, however they can induce a large overhead or are not always applicable in case data changes. Furthermore, for certain applications (e.g. handling imp ===Projects In Progress===
  2 KB (213 words) - 13:32, 6 October 2023
• User:Dpalossi
  ...in Information Technology and Electrical Engineering from the ETH Zürich, in 2019. He is currently a Postdoctoral Researcher at the Integrated Systems L ===Projects In Progress===
  2 KB (232 words) - 18:27, 26 July 2022
• Pulse Oximetry Fachpraktikum
  ...of generating and acquiring signals used in 'photoplethysmography' (PPG). In this thesis, the goal is to '''create''' a new Fachpraktikum where students Each improvement step is compared in size and power with the previous version.
  3 KB (358 words) - 15:59, 18 February 2019
• Predictable Execution
  ...on the same chip as the host CPU, sharing a single DRAM. This has benefits in both programability and performance, due to the removal of the need for dat ...l-time guarantees can be provided, enabling the use of these architectures in a real-time setting.
  2 KB (286 words) - 18:48, 10 November 2020
• Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
  [[Category:In progress]] == Status: In Progress ==
  2 KB (226 words) - 14:22, 27 February 2024
• Implementation of a Cache Reliability Mechanism (1S/M)
  [[Category:In progress]] == Status: In Progress ==
  2 KB (267 words) - 14:22, 27 February 2024
• Talk:Main Page
  # Projects in Progress I suggest listing only 5 or so porjects here and link to Category:In progress
  824 bytes (125 words) - 20:14, 5 February 2015
• Fault-Tolerant Floating-Point Units (M)
  [[Category:In progress]] == Status: In Progress ==
  2 KB (273 words) - 14:23, 27 February 2024
• Reconfigurability of SHA-3 candidates
  In December 2010, the 5 finalists of the SHA-3 competition were announced. The : Interest in Cryptography
  2 KB (300 words) - 14:11, 13 March 2014
• Novel Metastability Mitigation Technique
  ...tching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power c ...against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passiv
  2 KB (203 words) - 18:03, 16 December 2022
• Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
  ...ty will first be investigated at a functional level before implementing it in a CMOS process. ===Status: In Progress ===
  2 KB (356 words) - 15:55, 6 May 2019
• User:Vivianep
  ...ckend for Snitch-based manycore platforms. Currently, I am pursuing a Ph.D in developing the software stack for novel architectures developed at IIS and ===Projects In Progress===
  2 KB (255 words) - 11:45, 12 March 2024
• Acceleration and Transprecision
  ...cient. Such accelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cr ===Projects In Progress===
  2 KB (275 words) - 17:05, 24 November 2023
• Ultra-low power sampling front-end for acquisition of physiological signals
  ...a switched capacitor circuit before converting it into the digital domain. In this thesis it will be possible to learn the whole the design cycle includi ===Status: In Progress ===
  2 KB (359 words) - 16:06, 6 May 2019

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