Difference between revisions of "Extension and Evaluation of TinyDMA (1-2S/B/2-3G)"
(Created page with "<!-- Creating Extension and Evaluation of TinyDMA (1-2S/B/2-3G) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2022...")
|Line 11:||Line 11:|
Revision as of 12:55, 21 June 2022
- Type: Bachelor / Semester Thesis or Group Project
- Professor: Prof. Dr. L. Benini
At IIS we are developing an architectural family of lightweight yet high-performance data movement engines. We call the configuration with the lowest area footprint TinyDMA.
Currently, TinyDMA is based on the AMBA AXI4 on-chip communication standard. Next to AXI4, simpler protocols are used to transfer data around the chip. We employ widely in our SoCs three of these protocols: AXI 4 Lite, TCDM, and Regbus. Switching to such a (or multiple) simpler protocol(s) will reduce the area of TinyDMA further.
TinyDMA only features the bare minimum hardware required to transport data over an AXI4 interconnect. This simplicity comes at a price: the legalization of the AXI transfers must be done in software.
In this project, you extend TinyDMA to feature at least one simple protocol (e.g. AXI4 Lite) next to the already existing support for AXI4. You will evaluate the consequences of this switch in terms of area/speed/power (in a highly advanced 12nm node) as well as the impact on key performance numbers (latency, throughput, ...).
- 40% RTL Design and Verification
- 20% Software / Driver / HAL writing (C)
- 40% Evaluation
- Interest in memory systems
- Experience with digital design in SystemVerilog as taught in VLSI I
- Preferred: Knowledge or experience with AXI and RISC-V