Difference between revisions of "Huawei Research"
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! style="width: 4%;"|Status !! style="width: 2%;"|Year !! style="width: 5%;"|Type !! style="width: 20%"|Project !! style="width: 40%"|Description !! style="width: 5%"|Topic !! style="width: 15%"|Workload Type || Contact
| open || 2022 || Internship || Digital VLSI Design Intern (ML Acceleration)|| We offer up to two internships from autumn on ML acceleration on Ascend. Details follow. If you are interested, get in contact. || AI Acceleration || digital VLSI design ||
| open || 2022 || Internship || Digital VLSI Design Intern (ML Acceleration)|| We offer up to two internships from autumn on ML acceleration on Ascend. Details follow. If you are interested, get in contact. || AI Acceleration || digital VLSI design || [mailto:firstname.lastname@example.org Renzo Andri]
| finished || 2021 || Semester Thesis || [[New RVV 1.0 Vector Instructions for Ara]] || Implementation and complimenting the Ara vector processor for full compliance of the RVV 1.0 Vector standard || Processor Design || digital VLSI design || [[:User:Mperotti | Matteo Perotti]] (ETH), Renzo Andri (Huawei),
Revision as of 14:14, 26 July 2022
About the Huawei Future Computing Laboratory
With 18 sites across Europe and 1500 researchers, Huawei’s European Research Institute (ERI) oversees fundamental and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. Huawei’s ERI includes the new Zurich Research Center (ZRC), located in Zurich, Switzerland. A major element of ZRC is a new research laboratory focused on fundamental research in the area of future computing systems (new hardware, new software, new algorithms).
The research work of the lab will be carried out not only by Huawei’s internal research staff but also by our academic research partners in universities across Europe. The lab will provide an “open research environment” where academics will be encouraged to visit and work on fundamental long-term research alongside Huawei staff in an environment that, like the best universities and research institutes, is open and conducive to such scientific work.
Available and On-Going Projects
We are inviting applications from students to conduct their master’s thesis work or an internship project at the Huawei Future Computing Lab in Zurich on these exciting new topics. We are open to discuss also other topics. We are also supervising master's and semester theses in collaboration with the Integrated Systems Laboratory. Feel free to contact us, we are happy to hear from you.
|open||2022||Internship||Digital VLSI Design Intern (ML Acceleration)||We offer up to two internships from autumn on ML acceleration on Ascend. Details follow. If you are interested, get in contact.||AI Acceleration||digital VLSI design||Renzo Andri|
|finished||2021||Semester Thesis||New RVV 1.0 Vector Instructions for Ara||Implementation and complimenting the Ara vector processor for full compliance of the RVV 1.0 Vector standard||Processor Design||digital VLSI design||Matteo Perotti (ETH), Renzo Andri (Huawei),|
|finished||2021||Semester Thesis||Digital VLSI Design (ML Acceleration)||Winograd has been exploited for efficient calculation of convolutions which are typically used in ML applications (e.g., image classification), a novel algorithm shows nice properties to use complex Winograd to further reduce the computational complexity. In this project, we would like to evaluate the actual benefits in HW by designing an accelerator exploiting the new algorithm.||AI Acceleration||digital VLSI design||Renzo Andri, TBD PhD student at IIS|
|finished||2021||Internship||Digital VLSI Design Intern (ML Acceleration)||Link to description||AI Acceleration||digital VLSI design||Renzo Andri|
|finished||2021||Internship||High-Performance Machine Learning Kernel Development||Link to description||AI Acceleration||hardware-level SW development||Renzo Andri, Lukas Cavigelli|
- Renzo Andri, firstname.lastname at huawei com
- Lukas Cavigelli, firstname.lastname at huawei com
Internship Digital VLSI Design for ML Acceleration (Taken)
This internship has been taken, if you are interested in similar topics, get in contact with us.
For the new ZRC Laboratory, we were looking for an outstanding Digital VLSI Design Intern. As a key member in our motivated and multicultural team, you will support to design and evaluate novel VLSI architectures for energy-efficient machine learning acceleration.
- Design and Implementation of Digital VLSI HW architecture (RTL) for Machine Learning Acceleration
- Mapping of data, parameters and computations from a ML framework to the HW Accelerator.
- Synthesis and Backend/Layout and gate-level power simulation
- Scientific evaluation and potential publication.
Requirements - Your background
- You are currently enrolled in a Master’s degree or PhD in electrical engineering, compute engineering or computer science, or any related fields at a reputable university; or you graduated within the last six months
- Solid Digital VLSI Design knowledge Front-end and preferably also Back-end (e.g., VLSI I-II)
- You have worked on a VLSI project (e.g., semester/master thesis at IIS) and used industry-standard tools like Design Compiler, Innovus, Modelsim or similar.
- Basic knowledge in computer arithmetics.
- Basic knowledge in machine learning is an asset.
- Strong coding and scripting skills (SystemVerilog/VHDL, Python, TCL, Bash etc.)
- Excellent communication and writing skills in English
Interested to develop with us the next generation of machine learning hardware, then apply here