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• ASIC Design of a Gaussian Message Passing Processor
  ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
  1 KB (210 words) - 08:34, 20 January 2021
• Analog
  ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor ...he field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless t
  3 KB (369 words) - 18:11, 1 March 2023
• ASIC Design of a Sigma Point Processor
  ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
  2 KB (265 words) - 08:34, 20 January 2021
• Android reliability governor
  Dynamic Reliability Management (DRM) techniques aims at trading-off processor performance with lifetime at run-time by modulating the working temperature
  4 KB (573 words) - 17:24, 9 February 2015
• Design of an LTE Module for the Internet of Things
  [[Category:Processor]]
  3 KB (335 words) - 14:20, 4 November 2019
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  9 KB (1,289 words) - 19:45, 24 March 2015
• Low-power Clock Generation Solutions for 65nm Technology
  operating voltage, the clock rate of such a processor will be between
  3 KB (466 words) - 19:37, 3 March 2016
• Evaluating the RiscV Architecture
  [[Category:Processor]]
  3 KB (374 words) - 16:24, 30 October 2020
• Hardware/software co-programming on the Parallella platform
  ...power platform similar to the Raspberry Pi. It features a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiph
  3 KB (501 words) - 14:26, 2 September 2015
• Gomeza old project1
  # Characterization of the time/memory overhead incurred by the inter-processor communication.
  3 KB (431 words) - 18:04, 28 January 2017
• Acceleration and Transprecision
  ...e the backbone of big data and scientific computing. While general purpose processor architectures such as Intel's x86 provide good performance across a wide va
  2 KB (275 words) - 17:05, 24 November 2023
• Linear Solvers for Image and Video Processing Applications
  #REDIRECT [[DMA Streaming Co-processor]]
  40 bytes (4 words) - 18:10, 14 April 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. ...n allows the programmer to share virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires t
  5 KB (716 words) - 13:43, 29 November 2019
• Vector Processor for In-Memory Computing
  ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design
  3 KB (443 words) - 13:10, 2 November 2015
• FFT-based Convolutional Network Accelerator
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  8 KB (1,145 words) - 11:30, 5 February 2016
• High-speed Scene Labeling on FPGA
  ...the types of layer in the ConvNet, interaction between a flow controlling processor (e.g. an ARM core on a Xilinx Zynq) and the programmable logic is foreseen. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  8 KB (1,197 words) - 18:18, 29 August 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  4 KB (554 words) - 17:57, 7 November 2017
• Digital Audio Processor for Cellular Applications
  ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
  1 KB (229 words) - 18:01, 29 March 2017
• Switched Capacitor Based Bandgap-Reference
  [[Category:Processor]]
  4 KB (471 words) - 11:13, 3 May 2018

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