Search results

Create the page "Physical Design" on this wiki! See also the search results found.

Page title matches

• Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
  <!-- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (1-2S/M) --> [[Category:Physical Design]]
  4 KB (530 words) - 10:50, 3 November 2023
• Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer
  #REDIRECT [[Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S))]]
  107 bytes (14 words) - 10:50, 3 November 2023
• Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S))
  #REDIRECT [[Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)]]
  106 bytes (14 words) - 10:50, 3 November 2023

Page text matches

• Main Page
  * [[Analog| Analog and Mixed Signal Design]] * [[:Category:Physical Characterization|Physical Characterization]]
  5 KB (540 words) - 12:31, 8 May 2024
• Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  The aim of this project is the design of a hardware architecture and VLSI implementation up-to 16 users over the same physical channel in the presence of several multipath components)
  5 KB (684 words) - 10:43, 6 November 2017
• Weekly Reports
  ...ne in the current week. Make sure to report results (if any) and inform of design decisions you have taken. Make sure you add technical insight when possible number of actually implemented interrupt sources in the physical
  7 KB (1,133 words) - 07:08, 7 October 2023
• Digital Transmitter for Mobile Communications
  ...ion coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver. ...as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and fina
  3 KB (382 words) - 20:00, 26 September 2017
• CPS Software-Configurable State-Machine
  ...ts are connected and operate and act collaboratively it is called a 'cyper-physical system' (CPS). ...ve power, this unit will not be a conventional fully synchronously clocked design: the configurable state-machine will be clocked on an event basis only.
  3 KB (418 words) - 11:24, 10 November 2017
• Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
  Bottom: Layout of the [[RazorEDGE]] physical layer baseband ASIC. The highlighted area is occupied by the SOVE block.]] One of the most challenging parts of the design is the channel equalizer and detector block which must be capable of handli
  2 KB (286 words) - 10:04, 18 February 2015
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
  In a classical GSM/EDGE implementation IR operations are distributed over Physical Layer (PHY), Layer 2 (L2)/ Layer 3 (L3), and erroneous RLC blocks are store ...se of external components. Naturally, this simplicity eases L2/L3 protocol design.
  3 KB (397 words) - 14:12, 27 May 2015
• IcySoC
  ...r many decades owing to the overwhelming success of the integrated circuit design using reliable transistors, particularly in Complementary Metal-Oxide-Semic ...as recognition, search and data mining, lend themselves readily for such a design philosophy. In fact, all of which can tolerate inaccuracies to varying exte
  4 KB (568 words) - 12:48, 9 February 2015
• Ultra Low Power Wake Up Radio for Wireless Sensor Network
  ...cognized as a fundamental enabling technology for a large variety of cyber-physical systems (CPS) applications in environmental monitoring, healthcare, securit * '''[[Design Review]]'''
  4 KB (613 words) - 19:54, 9 February 2015
• Integrated silicon photonic structures
  physical effect available in integrated photonics circuits has been a scientific and to optical design and simulations, having the designs fabricated, and perform photonic
  4 KB (608 words) - 13:58, 23 June 2021
• ASIC
  ...pplication Specific Integrated Circuit) project you will be working on the design of an integrated circuit. This will include: * The actual physical design of the integrated circuit
  1 KB (165 words) - 19:52, 10 February 2015
• Ambient RF Energy harvesting for Wireless Sensor Network
  ...cognized as a fundamental enabling technology for a large variety of cyber-physical systems (CPS) applications in environmental monitoring, healthcare, securit * '''[[Design Review]]'''
  3 KB (378 words) - 19:56, 9 February 2015
• Digital Transmitter for Cellular IoT
  ...otyping. This project will involve modeling in Matlab but mostly it is HDL design, synthesis, and FPGA testing. This project is a perfect opportunity to apply architectural design methods. The outcome is likely to be the first EC-GSM capable transmitter i
  3 KB (384 words) - 16:41, 17 July 2016
• Design of an LTE Module for the Internet of Things
  ...ework towards Category-0 devices. In a second stage you will implement the design in a hardware description language (HDL) and deploy it to the LTE transceiv : 50% FPGA Design
  3 KB (335 words) - 14:20, 4 November 2019
• Modeling FlooNoC in GVSoC (S/M)
  ...mance analysis. This makes it an invaluable tool in breaking the speed and design effort bottlenecks of traditional simulators and FPGA prototypes, while sti ...][4], distinguished for its low-latency, full AXI4 compatibility, and wide physical channels. Designed to address the high-bandwidth requirements of contempora
  4 KB (520 words) - 15:15, 4 December 2023
• Beat DigRF
  Bearing this in mind, a single chip Physical Layer (PHY) has been developed at the institute in the [[stoneEDGE]] projec ...nts. This project provides a good opportunity to dig deep into an existing design and hopefully give reason to refrain from using off-chip interfaces for on-
  2 KB (299 words) - 17:58, 14 April 2016
• Turbo Equalization for Cellular IoT
  .... In a next step this algorithm needs to be adapted towards the LTE Cat-M2 physical communication channels which support codeword repetitions. In the next phas * '''[[Design Review]]'''
  3 KB (450 words) - 11:43, 13 November 2018
• NextGenChannelDec
  ...r are well established in the majority of communication systems. While the physical baseband computation in the cellular LTE standard bases for example on Turb : 30% Architectural Design
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  ...r are well established in the majority of communication systems. While the physical baseband computation in the cellular LTE standard bases for example on Turb : 30% Architectural Design
  3 KB (418 words) - 14:01, 13 November 2020
• Self-Learning Drones based on Neural Networks
  ...] (mainly applied on games: e.g. Go and set of Atari Games) to a new cyber-physical use-case scenario. Drones are a promising example of machines which can lea Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the rel
  6 KB (828 words) - 16:26, 20 February 2018

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)