Pages with the most categories
From iis-projects
Showing below up to 50 results in range #301 to #350.
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- Optimizing the Pipeline in our Floating Point Architectures (1S) (8 categories)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (8 categories)
- Accelerator for Boosted Binary Features (8 categories)
- Extended Verification for Ara (8 categories)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (8 categories)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (8 categories)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (8 categories)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (8 categories)
- Android reliability governor (8 categories)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (8 categories)
- DC-DC Buck converter in 65nm CMOS (8 categories)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (8 categories)
- Compiler Profiling and Optimizing (8 categories)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (8 categories)
- SmartRing (8 categories)
- Towards global Brain-Computer Interfaces (8 categories)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 categories)
- VLSI Implementation of a 5G Ciphering Accelerator (8 categories)
- On-Device Federated Continual Learning on Nano-Drone Swarms (8 categories)
- RVfplib (8 categories)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (8 categories)
- DMA Streaming Co-processor (8 categories)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (8 categories)
- Energy Efficient AXI Interface to Serial Link Physical Layer (8 categories)
- Extending our FPU with Internal High-Precision Accumulation (M) (8 categories)
- FPGA-Based Digital Frontend for 3G Receivers (8 categories)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (8 categories)
- Radiation Testing of a PULP ASIC (8 categories)
- Efficient TNN compression (8 categories)
- A Wireless Sensor Network for a Smart Building Monitor and Control (8 categories)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 categories)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (8 categories)
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles (8 categories)
- Low-Dropout Regulators for Magnetic Resonance Imaging (8 categories)
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores (8 categories)
- Low Precision Ara for ML (8 categories)
- Efficient collective communications in FlooNoC (1M) (8 categories)
- Wireless Sensing With Long Range Comminication (LoRa) (8 categories)
- PREM Intervals and Loop Tiling (8 categories)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (8 categories)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (8 categories)
- Real-time View Synthesis using Image Domain Warping (8 categories)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 categories)
- Integration Of A Smart Vision System (8 categories)
- LightProbe - CNN-Based-Image-Reconstruction (8 categories)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (8 categories)
- Bluetooth Low Energy receiver in 65nm CMOS (8 categories)
- Edge Computing for Long-Term Wearable Biomedical Systems (8 categories)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (8 categories)
- All the flavours of FFT on MemPool (1-2S/B) (8 categories)
