Category:Digital
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Pages in category "Digital"
The following 200 pages are in this category, out of 617 total.
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- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Deep Learning for Brain-Computer Interface
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep neural networks for seizure detection
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Fused Multiply Add Floating Point Unit
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of a VLIW processor architecture based on RISC-V
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of an LTE Module for the Internet of Things
- Design of combined Ultrasound and Electromyography systems
- Design of combined Ultrasound and PPG systems
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Designing a Power Management Unit for PULP SoCs
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Development of a Rockfall Sensor Node
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Development of statistics and contention monitoring unit for PULP
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Beamforming for Ultrasound Imaging
- Digital Transmitter for Mobile Communications
- DigitalUltrasoundHead
- DMA Streaming Co-processor
- User:Dpalossi
E
- Edge Computing for Long-Term Wearable Biomedical Systems
- EEG artifact detection for epilepsy monitoring
- EEG artifact detection with machine learning
- EEG earbud
- EEG-based drowsiness detection
- Efficient collective communications in FlooNoC (1M)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Search Design for Hyperdimensional Computing
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN compression
- Efficient TNN Inference on PULP Systems
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy Efficient Autonomous UAVs
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Neutral Multi Sensors Wearable Device
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating the RiscV Architecture
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring NAS spaces with C-BRED
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fabian Schuiki
- Fast Accelerator Context Switch for PULP
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fast Simulation of Manycore Systems (1S)
- Fast Wakeup From Deep Sleep State
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- User:Fischeti
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA mapping of RPC DRAM
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- Frank K. Gürkaynak
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Harald Kröll
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator for Model Predictive Controller
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Hardware/software co-programming on the Parallella platform
- Hardware/software codesign neural decoding algorithm for “neural dust”
- HERO: TLB Invalidation
- Heroino: Design of the next CORE-V Microcontroller
- Herschmi
- User:Herschmi
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Huawei Research
- Human Intranet
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- IBM Research
- Image and Video Processing
- Image Sensor Interface and Pre-processing
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a NB-IoT Positioning System
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Improving our Smart Camera System
- Improving Resiliency of Hyperdimensional Computing
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- In-ear EEG signal acquisition
- Indoor Positioning with Bluetooth
- Indoor Smart Tracking of Hospital instrumentation
- Infrared Wake Up Radio
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integrating Hardware Accelerators into Snitch (1S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integration Of A Smart Vision System
- Intelligent Disaster Early-Warning System (1-2S/M)
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)