Difference between revisions of "Category:Bachelor Thesis"
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Revision as of 15:13, 11 November 2020
Pages in category "Bachelor Thesis"
The following 75 pages are in this category, out of 75 total.
A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced Data Movers for Modern Neural Networks
- Advanced EEG glasses
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- All the flavours of FFT on MemPool (1-2S/B)
- Analog building blocks for mmWave manipulation
- ASIC Development of 5G-NR LDPC Decoder
- ASR-Waveformer
B
C
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
D
- DC-DC Buck converter in 65nm CMOS
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- Digital Control of a DC/DC Buck Converter
E
- EEG earbud
- EEG-based drowsiness detection
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Evaluating An Ultra low Power Vision Node
- Event-Driven Vision on an embedded platform
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
I
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementing A Low-Power Sensor Node Network
- Improved Reacquisition for the 5G Cellular IoT
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- In-ear EEG signal acquisition
- Integration Of A Smart Vision System
- IP-Based SoC Generation and Configuration (1-3S/B)
O
R
T
- Ternary Neural Networks for Face Recognition
- Testbed Design for Self-sustainable IoT Sensors
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
