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Revision as of 09:57, 29 July 2020
Contents
Contact Information
Paul Scheffler
- e-mail: paulsc@iis.ee.ethz.ch
- ETZ K61
Thomas Benz
- e-mail: tbenz@iis.ee.ethz.ch
- ETZ K61
Nils Wistoff
- e-mail: nwistoff@iis.ee.ethz.ch
- ETZ K61
Projects
Available Projects
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Hypervisor Extension for Ariane (M)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
Projects In Progress
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
Completed Projects
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